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  • I2C Bus Master

    Reference Design

    I2C Bus Master

    Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device
    I2C Bus Master
  • UART Reference Design

    Reference Design

    UART Reference Design

    The UART reference design describes a fully configurable UART optimized for and implemented in a variety of Lattice devices.
    UART Reference Design
  • Platform Manager Utility Function Core IP

    IP Core

    Platform Manager Utility Function Core IP

    Supports Fault Logging and Enhanced Closed-loop Trim power management functions.
    Platform Manager Utility Function Core IP
  • ADC Temperature Measurement Readout

    Reference Design

    ADC Temperature Measurement Readout

    Demonstrates the input of ambient temperature using an input voltage developed using an external resistor/thermistor and interface to the on-chip ADC using I2C
    ADC Temperature Measurement Readout
  • Platform Manager Development Kit

    Board

    Platform Manager Development Kit

    No longer available - for reference only. For evaluation & development with the Platform Manager ( LPTM10-12107 - 208-ball ftBGA) + 35mm slide pots.
    Platform Manager Development Kit
  • ProcessorPM Development Kit

    Board

    ProcessorPM Development Kit

    No longer available - for reference only. Low-cost platform for evaluating and designing with the ProcessorPM (605 and 6AT6) power management device.
    ProcessorPM Development Kit
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