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  • CSI-2/DSI D-PHY Transmitter IP Core

    IP Core

    CSI-2/DSI D-PHY Transmitter IP Core

    The CSI-2/DSI D-PHY Transmitter Submodule IP is for applications requiring D-PHY transmitter in the FPGA logic & supports both high-speed & low power modes
    CSI-2/DSI D-PHY Transmitter IP Core
  • UART 16550 IP Core

    IP Core

    UART 16550 IP Core

    ​​Lattice UART16550 IP Core is designed for use in serial communication, supporting the RS-232, RS-422, RS-485, and Electronic Industries Association (EIA) standards, among others.​
    UART 16550 IP Core
  • ECP5 Versa Development Kit

    Board

    ECP5 Versa Development Kit

    Evaluate and develop for key connectivity features of the ECP5 FPGA, including PCI Express, Gigabit Ethernet, DDR3 and generic SERDES, includes numerous demos.
    ECP5 Versa Development Kit
  • ECP5-5G Versa Development Kit

    Board

    ECP5-5G Versa Development Kit

    Evaluate and develop for key connectivity features of the ECP5-5G FPGA, including PCI Express, Gigabit Ethernet, DDR3 and 5G SERDES, includes numerous demos.
  • PCI Express x1, x4 Root Complex Lite IP Core

    IP Core

    PCI Express x1, x4 Root Complex Lite IP Core

    Provides a PCI Express x1 and x4 root complex solution from the electrical SERDES interface, physical layer, data link layer and a minimum transaction layer in PCIe protocol stack
    PCI Express x1, x4 Root Complex Lite IP Core
  • FFT Compiler IP Core

    IP Core

    FFT Compiler IP Core

    The FFT Compiler IP Core can be configured to perform forward FFT, inverse FFT (IFFT), or port selectable forward/inverse FFT.
    FFT Compiler IP Core
  • FIR Filter Generator IP Core

    IP Core

    FIR Filter Generator IP Core

    This IP core is a widely configurable, multi-channel FIR filter, implemented using high performance sysDSP™ blocks available in Lattice devices.
    FIR Filter Generator IP Core
  • Sensor Interfacing and Preprocessing

    Reference Design

    Sensor Interfacing and Preprocessing

    Aggregates data from multiple I2C interfaces and performs preprocessing like buffering, timestamping and complex event triggering based on data analysis.
    Sensor Interfacing and Preprocessing
  • Simple Sigma-Delta ADC

    Reference Design

    Simple Sigma-Delta ADC

    Implements an Analog-to-Digital (ADC) using on-FPGA differntial LVDS inputs (or inexpensive analog comparitor). Save cost by eliminating external ADC devices.
    Simple Sigma-Delta ADC
  • SPI Slave to PWM Generation Reference Design

    Reference Design

    SPI Slave to PWM Generation Reference Design

    Sets the frequency and duty cycle of a PWM (Pulse-Width Modulator) using data from an external SPI master.
    SPI Slave to PWM Generation Reference Design
  • I2C Slave Peripheral using Embedded Function Block

    Reference Design

    I2C Slave Peripheral using Embedded Function Block

    Ready to use RTL code segment that implements intuitive interface between an external I2C master and the MachXO2 internal registers or memory extension in XO2
    I2C Slave Peripheral using Embedded Function Block
  • Power Sequencing with Fault Logging Demo

    Demo

    Power Sequencing with Fault Logging Demo

    Uses L-ASC10 to monitor, sequence four separate Power Planes from a central control point. Logs faults with timestamps. Expandable.
    Power Sequencing with Fault Logging Demo
  • ASC Bridge Board

    Board

    ASC Bridge Board

    Interface with multiple (1-3) L-ASC10 Evaluation boards for rapid prototyping, development and testing of Power Management tasks
    ASC Bridge Board
  • L-ASC10 Breakout Board

    Board

    L-ASC10 Breakout Board

    A versatile hardware platform for evaluating and designing with L-ASC10 devices. Connect and control with FPGAs via the ASC Bridge board.
    L-ASC10 Breakout Board
  • ADC Interface

    Reference Design

    ADC Interface

    Interfaces with the Texas Instruments (TI) ADS64XX family of ADCs via LatticeECP3 FPGA high-speed LVDS I/O
    ADC Interface
  • PHY Interface for PCI Express - PIPE

    IP Core

    PHY Interface for PCI Express - PIPE

    A standard interface between a PHY device and the Media Access (MAC) layer for PCI Express (PCIe) applications
    PHY Interface for PCI Express - PIPE
  • ECC Module Reference Design

    Reference Design

    ECC Module Reference Design

    Provides Single Error Correction - Double Error Detection (SECDED) capability based on a class of optimal minimum oddweight error parity codes
    ECC Module Reference Design
  • POWR1014A Breakout Board

    Board

    POWR1014A Breakout Board

    A simple low-cost board that provides complete I/O access to the Power Manager II (POWR1014A)+LEDs, Prototyping area and more.
    POWR1014A Breakout Board
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