Lattice Solutions

IP Core

Byte to Pixel Converter IP Core

Byte-to-Pixel Converter IP converts CSI-2/DSI standard based video payload packets from D-PHY Receiver Module output to pixel format.

CrossLink, CrossLinkPlus, CrossLink-NX, Certus-NX, CertusPro-NX, Avant-E, MachXO5-NX 

MIPI, Modular MIPI/D-PHY, Parallel Video, Video Tx/Rx, Lattice mVision, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Guidance Systems, Automotive, Space 

IP Core

CSI-2/DSI D-PHY Transmitter IP Core

The CSI-2/DSI D-PHY Transmitter Submodule IP is for applications requiring D-PHY transmitter in the FPGA logic & supports both high-speed & low power modes

CrossLink, CrossLinkPlus, CrossLink-NX, Certus-NX, CertusPro-NX, Avant-E, MachXO5-NX 

CSI-2, DSI, MIPI, Modular MIPI/D-PHY, Video Tx/Rx, Lattice mVision, AR / VR & Drones, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Guidance Systems, Automotive, Space 

IP Core

Pixel to Byte Converter IP Core

Converts one, two, four, six, eight, or ten pixels per pixel clock into MIPI D-PHY byte packet compatible format

CrossLink, CrossLinkPlus, CrossLink-NX, Certus-NX, CertusPro-NX, Avant-E, MachXO5-NX 

CSI-2, MIPI, Modular MIPI/D-PHY, Parallel Video, Video Tx/Rx, Lattice mVision, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Guidance Systems, Automotive 

IP Core

UART 16550 IP Core

Configurable UART port. Compatible with PC16550D. 7 or 8 bit data width, 1, 1.5, 2 stop bits for Tx. Multiple parity and baud rate options.

iCE40 UltraPlus, CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX 

Bus Controllers, UART, TOR Switch, Guidance Systems, Automotive, Space 

Board

ECP5 Versa Development Kit

Evaluate and develop for key connectivity features of the ECP5 FPGA, including PCI Express, Gigabit Ethernet, DDR3 and generic SERDES, includes numerous demos.

ECP5 / ECP5-5G 

Data Communication, Ethernet, PCIe, SERDES, SMA, Versa Connector, DDR SDRAM, TOR Switch, Guidance Systems 

Board

ECP5-5G Versa Development Kit

Evaluate and develop for key connectivity features of the ECP5-5G FPGA, including PCI Express, Gigabit Ethernet, DDR3 and 5G SERDES, includes numerous demos.

ECP5 / ECP5-5G 

Data Communication, Ethernet, PCIe, SERDES, SMA, Versa Connector, DDR SDRAM, Guidance Systems 

IP Core

PCI Express x1, x4 Root Complex Lite IP Core

Provides a PCI Express x1 and x4 root complex solution from the electrical SERDES interface, physical layer, data link layer and a minimum transaction layer in PCIe protocol stack

ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M 

Connectivity IP Suite, PCIe, PCIe IP Suite, Guidance Systems, Automotive 

IP Core

FFT Compiler IP Core

The FFT Compiler IP Core can be configured to perform forward FFT, inverse FFT (IFFT), or port selectable forward/inverse FFT.

ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M, LatticeXP2, Certus-NX, CertusPro-NX, MachXO5-NX, CrossLink-NX, Avant-E 

DSP IP Suite, Value IP Suite, Data Communication, DSP, Guidance Systems, Automotive 

IP Core

FIR Filter Generator IP Core

This IP core is a widely configurable, multi-channel FIR filter, implemented using high performance sysDSP™ blocks available in Lattice devices.

ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M, LatticeXP2, CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX, Avant-E 

DSP, DSP IP Suite, Value IP Suite, Guidance Systems, Automotive 

Reference Design

Sensor Interfacing and Preprocessing

Aggregates data from multiple I2C interfaces and performs preprocessing like buffering, timestamping and complex event triggering based on data analysis.

iCE40 UltraPlus, iCE40 Ultra / UltraLite, iCE40 LP/HX 

Accelerometer, Compass, Gyroscope, I2C, IrDA, Pressure Sensor, Signal Aggregation, SPI, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Guidance Systems, Space 

Reference Design

Simple Sigma-Delta ADC

Implements an Analog-to-Digital (ADC) using on-FPGA differntial LVDS inputs (or inexpensive analog comparitor). Save cost by eliminating external ADC devices.

MachXO, MachXO2, LatticeXP2, iCE40 UltraPlus 

ADC/DAC, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Guidance Systems 

Reference Design

SPI Slave to PWM Generation

Sets the frequency and duty cycle of a PWM (Pulse-Width Modulator) using data from an external SPI master.

MachXO2, iCE40 UltraPlus 

SPI, PWM, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Guidance Systems, Space 

Reference Design

I2C Slave Peripheral using Embedded Function Block

Ready to use RTL code segment that implements intuitive interface between an external I2C master and the MachXO2 internal registers or memory extension in XO2

MachXO2, MachXO3 

Bus Controllers, I2C, TOR Switch, Guidance Systems 

Demo

Power Sequencing with Fault Logging Demo

Uses L-ASC10 to monitor, sequence four separate Power Planes from a central control point. Logs faults with timestamps. Expandable.

Platform Manager 2 & L-ASC10, MachXO3 

Mixed-Signal, Power Management, TOR Switch, Guidance Systems, 5G 

Board

ASC Bridge Board

Interface with multiple (1-3) L-ASC10 Evaluation boards for rapid prototyping, development and testing of Power Management tasks

Platform Manager 2 & L-ASC10 

Mixed-Signal, Power Management, RS-232, Versa Connector, TOR Switch, Guidance Systems 

Board

L-ASC10 Breakout Board

A versatile hardware platform for evaluating and designing with L-ASC10 devices. Connect and control with FPGAs via the ASC Bridge board.

Platform Manager 2 & L-ASC10 

Mixed-Signal, Power Management, RS-232, TOR Switch, Guidance Systems 

Reference Design

ADC Interface

Interfaces with the Texas Instruments (TI) ADS64XX family of ADCs via LatticeECP3 FPGA high-speed LVDS I/O

LatticeECP3, LatticeECP2/M 

ADC/DAC, Guidance Systems, Space 

IP Core

PHY Interface for PCI Express - PIPE

A standard interface between a PHY device and the Media Access (MAC) layer for PCI Express (PCIe) applications

LatticeECP3, LatticeECP2/M 

PCIe, PCIe IP Suite, PCS, SERDES, Guidance Systems 

Reference Design

ECC Module Reference Design

Provides Single Error Correction - Double Error Detection (SECDED) capability based on a class of optimal minimum oddweight error parity codes

LatticeECP3 

Data CODEC, Data Communication, Guidance Systems, Space 

Board

POWR1014A Breakout Board

A simple low-cost board that provides complete I/O access to the Power Manager II (POWR1014A)+LEDs, Prototyping area and more.

Power Manager II 

Breakout, Mixed-Signal, Power Management, TOR Switch, Guidance Systems