PCS Pipe IP核

Features

LatticeECP3 PCS PIPE IP core (v4.1)

PIPE Selection

• Fully compliant to PIPE Rev 1.00 specification
• Standard PCI Express PHY interface allows for multiple IP sources
• Selectable 8-bit or 16-bit interface to transmit and receive PCI Express data
• Holding registers/FIFO for staging transmit and receive data
• Multiple x1 channel support

SERDES/PCS Selection

• Selectable SERDES quad location for LatticeECP3 devices
• Selectable x1, multiple x1or x4 PCI Express implementations
• Selectable SERDES channel for PCI Express x1 mode
• Clock/data recovery from the serial stream
• Direct disparity control for use in transmitting compliance pattern
• 8b10b encoder/decoder and error indication
• Receiver detection
• 2.5GT/s full-duplex rate per channel

LatticeECP2M PCS PIPE IP Core

PIPE Section

• Fully compliant to PIPE Ver_1.00
• Standard PCI Express PHY interface allows for multiple IP sources
• Selectable 8-bit or 16-bit interface to transmit and receive PCI Express data
• Holding registers/FIFOs for staging transmit and receive data

SERDES/PCS Section

• Selectable SERDES Quad location for LatticeECP2M50 and larger devices
• Selectable x1or x4 PCI Express implementations
• Selectable SERDES Channel for PCI Express x1 mode
• Clock/data recovery from the serial stream
• Direct disparity control for use in transmitting compliance pattern
• 8b10b encoder/decoder and error indication
• Receiver detection
• 2.5GT/s full-duplex rate per channel