CSI-2/DSI D-PHY Transmitter IP Core

Convert Parallel Formatted Data Streams to MIPI CSI-2/DSI

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The Lattice Semiconductor CSI-2/DSI D-PHY Transmitter IP Core converts data bytes from a requestor to either DSI or CSI-2 data format for the Lattice Avant™, Nexus™, and Nexus 2 platforms. The CSI-2/DSI D-PHY Transmitter Submodule IP is intended for applications that require a D-PHY transmitter in the FPGA logic.

Latest Resource Utilization details are available in the IP Core User Guide.

Features

  • Compliant with MIPI D-PHY v2.1, MIPI DSI v1.3, and MIPI CSI-2 v1.2 specifications.
  • Supports 1, 2, 3, or 4 MIPI D-PHY data lanes.
  • Supports DSI video modes.
  • Supports low-power (LP) mode during vertical and horizontal blanking.

Jump to

Block Diagram

CSI-2-DSI-DPHY-TransmitterExpand Image

Ordering Information

The CSI-2/DSI D-PHY Transmitter IP is provided at no additional cost with the Lattice Radiant™ software.​

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
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CSI-2/DSI D-PHY Transmitter Submodule IP - Lattice Diamond Software
FPGA-IPUG-02024 1.6 5/14/2021 PDF 2.3 MB
CSI-2/DSI D-PHY Transmitter IP Core - User Guide
FPGA-IPUG-02080 2.5 12/11/2025 PDF 2.7 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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CSI-2/DSI D-PHY Transmitter IP Core - Release Notes
FPGA-RN-02041 1.2 12/11/2025 PDF 284.5 KB

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