Mobile Industry Processor Interface (MIPI®) D-PHY was developed primarily to support camera and display interconnections in mobile devices, and it has become the industry’s primary high-speed PHY solution for these applications in smartphones today. It is typically used in conjunction with MIPI Camera Serial Interface-2 (CSI-2) and MIPI Display Serial Interface (DSI) protocol specifications. MIPI D-PHY meets the demanding requirements of low-power, low noise generation, and high noise immunity that mobile phone designs demand. MIPI D-PHY is a practical PHY for typical camera and display applications.
The Lattice Semiconductor CSI-2/DSI D-PHY Transmitter IP Core converts data bytes from a requestor to either DSI or CSI-2 data format for Lattice Semiconductor CrossLink™-NX, Certus™-NX, CertusPro™-NX, MachXO5™-NX, and Lattice Avant™ family devices.
Supports Both High-Speed and Low Power Modes - The payload data uses the high-speed mode whereas the control and status information are sent in low power mode.
Hard MIPI D-PHY Tx and Soft MIPI D-PHY Tx – Hard MIPI D-PHY Tx features maximum rate up to 2500 Mbps per lane available in CrossLink-NX devices only; while the Soft MIPI D-PHY Tx features maximum rate up to 1500 Mbps per lane for Crosslink-NX, Certus-NX, and CertusPro-NX devices.
Consists of Main and Optional Modules – The CSI-2/DSI D-PHY Transmitter IP Core consists of the Global Operation Module, the D-PHY Tx Wrapper Module, an optional Packet Formatter Module, an optional AXI4 Stream Device Receiver, and an optional LMMI Target Module.