Mobile Industry Processor Interface (MIPI®) D-PHY was developed primarily to support camera and display interconnections in mobile devices, and it has become the industry’s primary high-speed PHY solution for these applications in smartphones today. It is typically used in conjunction with MIPI Camera Serial Interface-2 (CSI-2) and MIPI Display Serial Interface (DSI) protocol specifications. MIPI D-PHY meets the demanding requirements of low-power, low noise generation, and high noise immunity that mobile phone designs demand. MIPI D-PHY is a practical PHY for typical camera and display applications.
The CSI-2/DSI D-PHY Transmitter Submodule IP is intended for use in applications that require a D-PHY transmitter in the FPGA logic. This IP supports both high-speed and low power modes. The payload data uses the high-speed mode whereas the control and status information are sent in low power mode. The number of D-PHY data lanes to be used for the transmission of data is configurable and supports 1, 2, 3, or 4 data lanes.