CSI-2/DSI D-PHY Transmitter IP Core

Convert Parallel Formatted Data Streams to MIPI CSI-2/DSI

Mobile Industry Processor Interface (MIPI®) D-PHY was developed primarily to support camera and display interconnections in mobile devices, and it has become the industry’s primary high-speed PHY solution for these applications in smartphones today. It is typically used in conjunction with MIPI Camera Serial Interface-2 (CSI-2) and MIPI Display Serial Interface (DSI) protocol specifications. MIPI D-PHY meets the demanding requirements of low-power, low noise generation, and high noise immunity that mobile phone designs demand. MIPI D-PHY is a practical PHY for typical camera and display applications.

The CSI-2/DSI D-PHY Transmitter Submodule IP is intended for use in applications that require a D-PHY transmitter in the FPGA logic. This IP supports both high-speed and low power modes. The payload data uses the high-speed mode whereas the control and status information are sent in low power mode. The number of D-PHY data lanes to be used for the transmission of data is configurable and supports 1, 2, 3, or 4 data lanes.

Features

  • Compliant with MIPI D-PHY v2.1, MIPI DSI v1.3 and MIPI CSI-2 v1.2 Specifications.
  • Supports 1, 2, 3, or 4 MIPI D-PHY data lanes.
  • Supports DSI video modes.
  • Supports low-power (LP) mode during vertical and horizontal blanking.
  • Supports periodic deskew calibration.

Block Diagram

CSI-2-DSI-DPHY-Transmitter

Performance and Size

IP Configuration for Nexus Family
Number of Lanes (Gear) IP Type Bit Rate Lane Bypass Packet Formatter LMMI AXI EBR Registers LUT2 High-Speed I/O Interfaces
4 (8) Hard
DPHY
1000 Mbps DIS DIS EN 0 294 549 1 x Hard D-PHY
4 (8) Soft
DPHY
1000 Mbps DIS DIS EN 0 330 575 5 x ODDRX4,
1 x ECLKDIV,
1 x ECLKSYNC
4 (8) Hard
DPHY
2500 Mbps DIS DIS EN 0 339 1226 1 x Hard D-PHY
4 (8) Soft
DPHY
1500 Mbps DIS DIS EN 0 330 583 5 x ODDRX4,
1 x ECLKDIV,
1 x ECLKSYNC
4 (8) Hard
DPHY
2500 Mbps DIS EN EN 0 530 1522 1 x Hard D-PHY
4 (8) Soft
DPHY
1500 Mbps DIS DIS DIS 0 330 639 5 x ODDRX4,
1 x ECLKDIV,
1 x ECLKSYNC
4 (8) Hard
DPHY
2500 Mbps EN EN EN 0 362 388 1 x Hard D-PHY
4 (8) Soft
DPHY
1500 Mbps EN DIS DIS 0 182 188 5 x ODDRX4,
1 x ECLKDIV,
1 x ECLKSYNC

1. All other settings are default.
2. The distributed RAM utilization is accounted for in the total LUT4s utilization. The actual LUT4 utilization is distribution among logic, distributed RAM, and ripple logic



IP Configuration for CrossLink Family
IP User-Configurable Parameters Registers Slices LUTs sysMEM EBRs MIPI D-PHY Target fMAX(MHz) Actual fMAX(MHz)
CSI-2 Gear 16
4-lane Non-continuous clock 517 987 1496 0 1 93.75 114.71
2-lane Non-continuous clock 364 605 936 0 1 93.75 103.91
1-lane Non-continuous clock 309 484 758 0 1 93.75 133.35
4-lane Continuous clock 509 937 1433 0 1 93.75 122.91
2-lane Continuous clock 356 561 873 0 1 93.75 108.86
1-lane Continuous clock 301 443 695 0 1 93.75 129.87
CSI-2 Gear 8
4-lane Non-continuous clock 519 648 989 0 1 150 152.55
2-lane Non-continuous clock 336 452 699 0 1 150 154.27
1-lane Non-continuous clock 276 385 587 0 1 150 149.99
4-lane Continuous clock 511 620 974 0 1 150 152.93
2-lane Continuous clock 328 424 657 0 1 150 153.61
1-lane Continuous clock 268 357 545 0 1 150 150.83
DSI Gear 16
4-lane Non-continuous clock 656 2901 5548 0 1 93.75 109
2-lane Non-continuous clock 438 1617 2960 0 1 93.75 132.2
1-lane Non-continuous clock 334 937 1683 0 1 93.75 117.84
4-lane Continuous clock 648 2856 5485 0 1 93.75 109.23
2-lane Continuous clock 430 1573 2897 0 1 93.75 135.46
1-lane Continuous clock 326 896 1620 0 1 93.75 128.09
DSI Gear 8
4-lane Non-continuous clock 659 2676 5125 0 1 112.5 118
2-lane Non-continuous clock 447 1546 2836 0 1 150 157.11
1-lane Non-continuous clock 331 834 1513 0 1 93.75 120.12
4-lane Continuous clock 651 2653 5083 0 1 93.75 103.85
2-lane Continuous clock 439 1518 2794 0 1 150 150.92
1-lane Continuous clock 323 806 1471 0 1 112.5 128.32

1. Performance and utilization data target an LIF-MD6000-6MG81I device using Lattice Diamond 3.9 and Lattice Synthesis Engine software. Performance may vary when using a different software version or targeting a different device density or speed grade within the CrossLink family. This does not show all possible configurations of the D-PHY Transmitter IP.
2. The fMAX values are based on byte clock and may vary depending on the complete top level-design.
3. The distributed RAM utilization is accounted for in the total LUT4 utilization. The actual LUT4 utilization is distribution among logic, distributed RAM, and ripple logic.

Ordering Information

  Part Number
Device Family Single Design Multi-Site Subscription
Avant-E DPHY-TX-AVE-U DPHY-TX-AVE-UT DPHY-TX-AVE-US
MachXO5-NX DPHY-TX-XO5-U DPHY-TX-XO5-UT DPHY-TX-XO5-US
CertusPro-NX DPHY-TX-CPNX-U DPHY-TX-CPNX-UT DPHY-TX-CPNX-US
Certus-NX DPHY-TX-CTNX-U DPHY-TX-CTNX-UT DPHY-TX-CTNX-US
CrossLink-NX DPHY-TX-CNX-U DPHY-TX-CNX-UT DPHY-TX-CNX-US

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

To find out how to purchase the CSI-2/D-PHY Transmitter IP core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
CSI/DSI DPHY TX IP Core - Lattice Radiant Sofware
FPGA-IPUG-02080 2.0 7/19/2023 PDF 1.5 MB
CSI-2/DSI D-PHY Transmitter Submodule IP - Lattice Diamond Software
FPGA-IPUG-02024 1.6 5/14/2021 PDF 2.3 MB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.