CSI-2/DSI D-PHY Transmitter IP Core

Convert Parallel Formatted Data Streams to MIPI CSI-2/DSI

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The Lattice Semiconductor CSI-2/DSI D-PHY Transmitter IP Core converts data bytes from a requestor to either DSI or CSI-2 data format for Lattice Semiconductor CrossLink™-NX, Certus™-NX, CertusPro™-NX, MachXO5™-NX, and Lattice Avant™ family devices. The CSI-2/DSI D-PHY Transmitter Submodule IP is intended for applications that require a D-PHY transmitter in the FPGA logic. This IP supports both high-speed (HS) and low power (LP) modes. The payload data uses the high-speed mode whereas the control and status information are sent in low power mode.

Resource Utilization details are available in the IP Core User Guide.

Features

  • Compliant with MIPI D-PHY v2.1, MIPI DSI v1.3, and MIPI CSI-2 v1.2 specifications.
  • Supports 1, 2, 3, or 4 MIPI D-PHY data lanes
  • Supports DSI video modes
  • Supports low-power (LP) mode during vertical and horizontal blankin
  • Option for AXI4-stream interface

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Block Diagram

CSI-2-DSI-DPHY-TransmitterExpand Image

Resource Utilization

IP Configuration for Nexus Family
Number of Lanes (Gear) IP Type Bit Rate Lane Bypass Packet Formatter LMMI AXI EBR Registers LUT2 High-Speed I/O Interfaces
4 (8) Hard
DPHY		 1000 Mbps DIS DIS EN 0 294 549 1 x Hard D-PHY
4 (8) Soft
DPHY		 1000 Mbps DIS DIS EN 0 330 575 5 x ODDRX4,
1 x ECLKDIV,
1 x ECLKSYNC
4 (8) Hard
DPHY		 2500 Mbps DIS DIS EN 0 339 1226 1 x Hard D-PHY
4 (8) Soft
DPHY		 1500 Mbps DIS DIS EN 0 330 583 5 x ODDRX4,
1 x ECLKDIV,
1 x ECLKSYNC
4 (8) Hard
DPHY		 2500 Mbps DIS EN EN 0 530 1522 1 x Hard D-PHY
4 (8) Soft
DPHY		 1500 Mbps DIS DIS DIS 0 330 639 5 x ODDRX4,
1 x ECLKDIV,
1 x ECLKSYNC
4 (8) Hard
DPHY		 2500 Mbps EN EN EN 0 362 388 1 x Hard D-PHY
4 (8) Soft
DPHY		 1500 Mbps EN DIS DIS 0 182 188 5 x ODDRX4,
1 x ECLKDIV,
1 x ECLKSYNC

1. All other settings are default.
2. The distributed RAM utilization is accounted for in the total LUT4s utilization. The actual LUT4 utilization is distribution among logic, distributed RAM, and ripple logic



IP Configuration for Crosslink Family
LIFCL-40-BCG400
Number of Lanes (Gear) IP Type Bit Rate Lane Bypass Packet Formatter LMMI AXI EBR Registers LUT2 High-Speed I/O Interfaces
4 (8) Hard
DPHY		 1000 Mbps DIS DIS EN 0 294 549 1 x Hard D-PHY
4 (8) Soft
DPHY		 1000 Mbps DIS DIS EN 0 330 575 5 x ODDRX4,
1 x ECLKDIV,
1 x ECLKSYNC
4 (16) Hard
DPHY		 2500 Mbps DIS DIS EN 0 339 1226 1 x Hard D-PHY
4 (8) Soft
DPHY		 1500 Mbps DIS DIS EN 0 330 583 5 x ODDRX4,
1 x ECLKDIV,
1 x ECLKSYNC
4 (8) Hard
DPHY		 2500 Mbps DIS EN EN 0 530 1522 1 x Hard D-PHY
4 (8) Soft
DPHY		 1500 Mbps DIS DIS DIS 0 330 639 5 x ODDRX4,
1 x ECLKDIV,
1 x ECLKSYNC
4 (16) Hard
DPHY		 2500 Mbps EN EN EN 0 362 388 1 x Hard D-PHY
4 (8) Soft
DPHY		 1500 Mbps EN DIS DIS 0 182 188 5 x ODDRX4,
1 x ECLKDIV,
1 x ECLKSYNC

1. All other settings are default.
2. The distributed RAM utilization is accounted for in the total LUT4s utilization. The actual LUT4 utilization is distribution among logic, distributed RAM, and ripple logic.

Ordering Information

  Part Number
Device Family Multi-site Perpetual Single Seat Annual
Avant-G DPHY-TX-AVG-UT DPHY-TX-AVG-US
Avant-X DPHY-TX-AVX-UT DPHY-TX-AVX-US
Avant-E DPHY-TX-AVE-UT DPHY-TX-AVE-US
MachXO5-NX DPHY-TX-XO5-UT DPHY-TX-XO5-US
CertusPro-NX DPHY-TX-CPNX-UT DPHY-TX-CPNX-US
CrossLink-NX DPHY-TX-CNX-UT DPHY-TX-CNX-US
Certus-NX DPHY-TX-CTNX-UT DPHY-TX-CTNX-US
Bundled MIPI-BNDL-UT MIPI-BNDL-US

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
CSI-2/DSI D-PHY Transmitter Submodule IP - Lattice Diamond Software
FPGA-IPUG-02024 1.6 5/14/2021 PDF 2.3 MB
CSI/DSI D-PHY Transmitter IP Core - Lattice Radiant Sofware
FPGA-IPUG-02080 2.2 8/26/2024 PDF 1.7 MB

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