CSI-2/DSI D-PHY Transmitter IP Core

Convert Parallel Formatted Data Streams to MIPI CSI-2/DSI

Mobile Industry Processor Interface (MIPI®) D-PHY was developed primarily to support camera and display interconnections in mobile devices, and it has become the industry’s primary high-speed PHY solution for these applications in smartphones today. It is typically used in conjunction with MIPI Camera Serial Interface-2 (CSI-2) and MIPI Display Serial Interface (DSI) protocol specifications. MIPI D-PHY meets the demanding requirements of low-power, low noise generation, and high noise immunity that mobile phone designs demand. MIPI D-PHY is a practical PHY for typical camera and display applications.

The Lattice Semiconductor CSI-2/DSI D-PHY Transmitter IP Core converts data bytes from a requestor to either DSI or CSI-2 data format for Lattice Semiconductor CrossLink™-NX, Certus™-NX, CertusPro™-NX, MachXO5™-NX, and Lattice Avant™ family devices.

Supports Both High-Speed and Low Power Modes - The payload data uses the high-speed mode whereas the control and status information are sent in low power mode.

Hard MIPI D-PHY Tx and Soft MIPI D-PHY Tx – Hard MIPI D-PHY Tx features maximum rate up to 2500 Mbps per lane available in CrossLink-NX devices only; while the Soft MIPI D-PHY Tx features maximum rate up to 1500 Mbps per lane for Crosslink-NX, Certus-NX, and CertusPro-NX devices.

Consists of Main and Optional Modules – The CSI-2/DSI D-PHY Transmitter IP Core consists of the Global Operation Module, the D-PHY Tx Wrapper Module, an optional Packet Formatter Module, an optional AXI4 Stream Device Receiver, and an optional LMMI Target Module.

Features

  • Compliant with MIPI D-PHY v2.1, MIPI DSI v1.3 and MIPI CSI-2 v1.2 Specifications.
  • Supports 1, 2, 3, or 4 MIPI D-PHY data lanes.
  • Supports DSI video modes.
  • Supports low-power (LP) mode during vertical and horizontal blanking.
  • Supports periodic deskew calibration.

Block Diagram

Resource Utilization

IP Configuration for Nexus Family
Number of Lanes (Gear) IP Type Bit Rate Lane Bypass Packet Formatter LMMI AXI EBR Registers LUT2 High-Speed I/O Interfaces
4 (8) Hard
DPHY
1000 Mbps DIS DIS EN 0 294 549 1 x Hard D-PHY
4 (8) Soft
DPHY
1000 Mbps DIS DIS EN 0 330 575 5 x ODDRX4,
1 x ECLKDIV,
1 x ECLKSYNC
4 (8) Hard
DPHY
2500 Mbps DIS DIS EN 0 339 1226 1 x Hard D-PHY
4 (8) Soft
DPHY
1500 Mbps DIS DIS EN 0 330 583 5 x ODDRX4,
1 x ECLKDIV,
1 x ECLKSYNC
4 (8) Hard
DPHY
2500 Mbps DIS EN EN 0 530 1522 1 x Hard D-PHY
4 (8) Soft
DPHY
1500 Mbps DIS DIS DIS 0 330 639 5 x ODDRX4,
1 x ECLKDIV,
1 x ECLKSYNC
4 (8) Hard
DPHY
2500 Mbps EN EN EN 0 362 388 1 x Hard D-PHY
4 (8) Soft
DPHY
1500 Mbps EN DIS DIS 0 182 188 5 x ODDRX4,
1 x ECLKDIV,
1 x ECLKSYNC

1. All other settings are default.
2. The distributed RAM utilization is accounted for in the total LUT4s utilization. The actual LUT4 utilization is distribution among logic, distributed RAM, and ripple logic



IP Configuration for Crosslink Family
LIFCL-40-BCG400
Number of Lanes (Gear) IP Type Bit Rate Lane Bypass Packet Formatter LMMI AXI EBR Registers LUT2 High-Speed I/O Interfaces
4 (8) Hard
DPHY
1000 Mbps DIS DIS EN 0 294 549 1 x Hard D-PHY
4 (8) Soft
DPHY
1000 Mbps DIS DIS EN 0 330 575 5 x ODDRX4,
1 x ECLKDIV,
1 x ECLKSYNC
4 (16) Hard
DPHY
2500 Mbps DIS DIS EN 0 339 1226 1 x Hard D-PHY
4 (8) Soft
DPHY
1500 Mbps DIS DIS EN 0 330 583 5 x ODDRX4,
1 x ECLKDIV,
1 x ECLKSYNC
4 (8) Hard
DPHY
2500 Mbps DIS EN EN 0 530 1522 1 x Hard D-PHY
4 (8) Soft
DPHY
1500 Mbps DIS DIS DIS 0 330 639 5 x ODDRX4,
1 x ECLKDIV,
1 x ECLKSYNC
4 (16) Hard
DPHY
2500 Mbps EN EN EN 0 362 388 1 x Hard D-PHY
4 (8) Soft
DPHY
1500 Mbps EN DIS DIS 0 182 188 5 x ODDRX4,
1 x ECLKDIV,
1 x ECLKSYNC

1. All other settings are default.
2. The distributed RAM utilization is accounted for in the total LUT4s utilization. The actual LUT4 utilization is distribution among logic, distributed RAM, and ripple logic.

Ordering Information

  Part Number
Device Family Multi-site Perpetual Single Seat Annual
Avant-G DPHY-TX-AVG-UT DPHY-TX-AVG-US
Avant-X DPHY-TX-AVX-UT DPHY-TX-AVX-US
Avant-E DPHY-TX-AVE-UT DPHY-TX-AVE-US
MachXO5-NX DPHY-TX-XO5-UT DPHY-TX-XO5-US
CertusPro-NX DPHY-TX-CPNX-UT DPHY-TX-CPNX-US
Certus-NX DPHY-TX-CTNX-UT DPHY-TX-CTNX-US
CrossLink-NX DPHY-TX-CNX-UT DPHY-TX-CNX-US

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

To find out how to purchase the CSI-2/D-PHY Transmitter IP core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
CSI-2/DSI D-PHY Transmitter Submodule IP - Lattice Diamond Software
FPGA-IPUG-02024 1.6 5/14/2021 PDF 2.3 MB
CSI/DSI DPHY TX IP Core - Lattice Radiant Sofware
FPGA-IPUG-02080 2.1 2/2/2024 PDF 1.7 MB

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