CSI-2/DSI D-PHY发送器

将并行数据流转换为MIPI CSI-2/DSI

移动行业处理器接口(MIPI®)D-PHY 主要开发用于支持移动设备的摄像头和显示器互连,并成为行业主流的高速PHY解决方案,适用于智能手机应用。它通常用于MIPI摄像机串行接口-2(CSI-2)和MIPI显示串行接口(DSI)协议的互连。MIPI D-PHY满足手机设计对于低功耗、低噪声、高噪声免疫的要求。MIPI D-PHY是用于典型摄像头和显示应用的非常常用的PHY。

Lattice CSI-2/DSI D-PHY发送器子模块IP提供用于Lattice CrossLink系列器件的并行数据到MIPI CSI-2/DSI的数据转换。适用于可穿戴设备、平板电脑、人机界面、医疗设备和其他许多应用场景。

特性

  • 符合MIPI DSI v1.1,MIPI CSI-2 v1.1和MIPI D-PHY v1.1规范
  • 支持MIPI DSI和MIPI CSI-2接口,速率高达10 Gb/s
  • 支持1,2 或4条MIPI D-PHY数据通道
  • 支持仅DSI数据包的非突发模式与同步事件传输
  • 提供垂直和水平消隐下的LP(低功耗)模式

框图

CSI-2-DSI-DPHY-Transmitter

Performance and Size

IP Configuration for Nexus Family
Number of Lanes (Gear) IP Type Bit Rate Lane Bypass Packet Formatter LMMI AXI EBR Registers LUT2 High-Speed I/O Interfaces
4 (8) Hard
DPHY
1000 Mbps DIS DIS EN 0 294 549 1 x Hard D-PHY
4 (8) Soft
DPHY
1000 Mbps DIS DIS EN 0 330 575 5 x ODDRX4,
1 x ECLKDIV,
1 x ECLKSYNC
4 (8) Hard
DPHY
2500 Mbps DIS DIS EN 0 339 1226 1 x Hard D-PHY
4 (8) Soft
DPHY
1500 Mbps DIS DIS EN 0 330 583 5 x ODDRX4,
1 x ECLKDIV,
1 x ECLKSYNC
4 (8) Hard
DPHY
2500 Mbps DIS EN EN 0 530 1522 1 x Hard D-PHY
4 (8) Soft
DPHY
1500 Mbps DIS DIS DIS 0 330 639 5 x ODDRX4,
1 x ECLKDIV,
1 x ECLKSYNC
4 (8) Hard
DPHY
2500 Mbps EN EN EN 0 362 388 1 x Hard D-PHY
4 (8) Soft
DPHY
1500 Mbps EN DIS DIS 0 182 188 5 x ODDRX4,
1 x ECLKDIV,
1 x ECLKSYNC

1. All other settings are default.
2. The distributed RAM utilization is accounted for in the total LUT4s utilization. The actual LUT4 utilization is distribution among logic, distributed RAM, and ripple logic



IP Configuration for CrossLink Family
IP User-Configurable Parameters Registers Slices LUTs sysMEM EBRs MIPI D-PHY Target fMAX(MHz) Actual fMAX(MHz)
CSI-2 Gear 16
4-lane Non-continuous clock 517 987 1496 0 1 93.75 114.71
2-lane Non-continuous clock 364 605 936 0 1 93.75 103.91
1-lane Non-continuous clock 309 484 758 0 1 93.75 133.35
4-lane Continuous clock 509 937 1433 0 1 93.75 122.91
2-lane Continuous clock 356 561 873 0 1 93.75 108.86
1-lane Continuous clock 301 443 695 0 1 93.75 129.87
CSI-2 Gear 8
4-lane Non-continuous clock 519 648 989 0 1 150 152.55
2-lane Non-continuous clock 336 452 699 0 1 150 154.27
1-lane Non-continuous clock 276 385 587 0 1 150 149.99
4-lane Continuous clock 511 620 974 0 1 150 152.93
2-lane Continuous clock 328 424 657 0 1 150 153.61
1-lane Continuous clock 268 357 545 0 1 150 150.83
DSI Gear 16
4-lane Non-continuous clock 656 2901 5548 0 1 93.75 109
2-lane Non-continuous clock 438 1617 2960 0 1 93.75 132.2
1-lane Non-continuous clock 334 937 1683 0 1 93.75 117.84
4-lane Continuous clock 648 2856 5485 0 1 93.75 109.23
2-lane Continuous clock 430 1573 2897 0 1 93.75 135.46
1-lane Continuous clock 326 896 1620 0 1 93.75 128.09
DSI Gear 8
4-lane Non-continuous clock 659 2676 5125 0 1 112.5 118
2-lane Non-continuous clock 447 1546 2836 0 1 150 157.11
1-lane Non-continuous clock 331 834 1513 0 1 93.75 120.12
4-lane Continuous clock 651 2653 5083 0 1 93.75 103.85
2-lane Continuous clock 439 1518 2794 0 1 150 150.92
1-lane Continuous clock 323 806 1471 0 1 112.5 128.32

1. Performance and utilization data target an LIF-MD6000-6MG81I device using Lattice Diamond 3.9 and Lattice Synthesis Engine software. Performance may vary when using a different software version or targeting a different device density or speed grade within the CrossLink family. This does not show all possible configurations of the D-PHY Transmitter IP.
2. The fMAX values are based on byte clock and may vary depending on the complete top level-design.
3. The distributed RAM utilization is accounted for in the total LUT4 utilization. The actual LUT4 utilization is distribution among logic, distributed RAM, and ripple logic.

订购信息

CSI-2 DSI D-PHY发送器IP核可在Diamond设计软件中免费使用。

若要在Radiant设计软件中使用该IP,则需购买:

产品系列 订购编号 描述
CrossLink-NX DPHY-TX-CNX-U 单次设计许可
CrossLink-NX DPHY-TX-CNX-UT 多站点许可

文档

快速参考
标题 编号 版本 日期 格式 文件大小
选择全部
CSI/DSI DPHY TX IP Core - Lattice Radiant Sofware
FPGA-IPUG-02080 2.0 7/19/2023 PDF 1.5 MB
CSI-2/DSI D-PHY Transmitter Submodule IP - Lattice Diamond Software
FPGA-IPUG-02024 1.6 5/14/2021 PDF 2.3 MB