Smart Munitions

Increased Autonomy with Sensor Fusion

Launched from various platforms, smart munitions are advanced systems that rely on sophisticated sensors and signal processing to offer a wide variety of functions and features from GPS-denied environments to autonomous detection and classification. Lattice FPGAs implement complex signal processing algorithms including object detection and classification and enable seamless sensor connectivity and management of data secure data flow to a wide variety of sensors and handle secure, anti-tamper communication and control. 

  • Low power FPGAs to meet extended temperature and other harsh environmental constraints
  • Industry leading fast, secure boot with state of the art security and robust encryption to meet domain specific safety, security and reliability requirements
  • Sophisticated tool flow with redundancy, isolation design flow in support of Design Assurance Levels.

Features

  • Lattice FPGAs with small form factor, low power deliver a robust sensor and signal processing solution with adaptable parallel / serial interfaces and high speed transceiver connections to analog front ends while meeting SWaP-C requirements.
  • Industry leading advanced security features including AES256-GCM, ECDSA 256-521 & RSA 2048-4096 with post quantum resilience, anti-tamper and hardened PUF to secure bitstream and user data and support upgradability to tackle future needs and evolving threats.
  • State of the art security features including industry’s fastest secure boot and hardware security measures enable robust security protocols withing the constrained environment and reliable operation at extremely high speeds.

Jump to

Example-Applications

Actuator Control

  • Single-chip non-volatile FPGAs with 2ms bitstream verification, authentication and boot-up time
  • Embedded A/D converters for sensor fusion, feedback and sensing
  • Packages as small as 6x6 mm, and in ball-pitch options of 0.5 and 0.8 mm 

Telemetry

  • Power efficient, highly reliable system control and monitoring
  • Optimum integration level with embedded MCU and ADCs
  • Utmost control and flexibility in sense and control of rea-time data

Trigger

  • Critical bitstream verification and safety compliance
  • ECDSA bitstream authentication, coupled with robust AES-256 encryption
  • Robust flash-based FPGAs ideal for sensor processing and control

Reference Design

冗余电源管理

Reference Design

冗余电源管理

Uses a Lattice Power Manager II device to achieve Redundant Power Supply Management using the power supply OR’ing technique
冗余电源管理
SPI Slave 到 PWM 产生

Reference Design

简单的Σ-Δ ADC

Reference Design

简单的Σ-Δ ADC

Implements an Analog-to-Digital (ADC) using on-FPGA differntial LVDS inputs (or inexpensive analog comparitor). Save cost by eliminating external ADC devices.
简单的Σ-Δ ADC
使用嵌入式功能块的I2C从外设

Reference Design

使用嵌入式功能块的I2C从外设

Ready to use RTL code segment that implements intuitive interface between an external I2C master and the MachXO2 internal registers or memory extension in XO2
使用嵌入式功能块的I2C从外设

Demo

拥有故障记录功能的电源时序演示

演示

拥有故障记录功能的电源时序演示

使用L-ASC10监视和控制来自中心控制点的四个独立电源平面。带时间戳的故障记录。可扩展。
拥有故障记录功能的电源时序演示

IP Cores

FFT 编译器

IP Core

FFT 编译器

The FFT Compiler IP Core can be configured to perform forward FFT, inverse FFT (IFFT), or port selectable forward/inverse FFT.
FFT 编译器
FIR 滤波器生成器

IP Core

FIR 滤波器生成器

可灵活配置的多通道FIR滤波器。最多支持256个通道,每个拥有2048个抽头。输入和系数宽度为4至32位。
FIR 滤波器生成器
PCI Express x1、x4 Root Complex Lite IP核

IP Core

PCI Express x1、x4 Root Complex Lite IP核

Provides a PCI Express x1 and x4 root complex solution from the electrical SERDES interface, physical layer, data link layer and a minimum transaction layer in PCIe protocol stack
PCI Express x1、x4 Root Complex Lite IP核

Development Kits & Boards

ECP5 Versa开发套件

Board

ECP5 Versa开发套件

设计工程师可使用ECP5 Versa开发套件快速评估ECP5 FPGA关键的互连功能,包括PCI Express、千兆以太网、DDR3和通用SERDES的性能。
ECP5 Versa开发套件
ECP5-5G  Versa开发套件

Board

ECP5-5G Versa开发套件

评估PCI Express 2.0、千兆级以太网、DDR3和ECP5-5G SERDES的性能
L-ASC10分线板

Board

L-ASC10分线板

L-ASC10(ASC)分线板是一款通用的硬件平台,适用于L-ASC10器件的评估和开发。本分线板须与Platform Manager 2开发套件一起使用。
L-ASC10分线板
POWR1014A分线板(Breakout Board)

Board

POWR1014A分线板(Breakout Board)

POWR1014A是一款低成本的分线板,可提供到Power Manager II (POWR1014A)、LED、实验区域的完整I/O访问,可通过USB供电和进行编程,同时莱迪思提供可下载的演示。
POWR1014A分线板(Breakout Board)

Documentation

快速参考
标题 编号 版本 日期 格式 文件大小
选择全部
Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform
FPGA-TN-02076 2.3 10/13/2025 PDF 806.2 KB
Multi-Boot User Guide for Nexus Platform
FPGA-TN-02145 2.4 8/27/2025 PDF 1.4 MB
Implementing JOTP-051-Compliant Safety Features in Lattice FPGAs
FPGA-TN-02150 1.1 3/15/2021 PDF 855.2 KB
标题 编号 版本 日期 格式 文件大小
选择全部
Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform
FPGA-TN-02076 2.3 10/13/2025 PDF 806.2 KB
Multi-Boot User Guide for Nexus Platform
FPGA-TN-02145 2.4 8/27/2025 PDF 1.4 MB
Implementing JOTP-051-Compliant Safety Features in Lattice FPGAs
FPGA-TN-02150 1.1 3/15/2021 PDF 855.2 KB