Lattice Solutions

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  • Tri-Speed Ethernet MAC Core IP

    IP Core

    Tri-Speed Ethernet MAC Core IP

    Transmits and receives data between a host processor and an Ethernet network. IEEE 802.3 compliant. Supports 10/100/1000 operation.
    Tri-Speed Ethernet MAC Core IP
  • KONDOR AX Development Board

    Board

    KONDOR AX Development Board

    ECP5 board for system design of HetNet, Industrial IoT, Cameras and Display applications
    KONDOR AX Development Board
  • ECP5 Versa Development Kit

    Board

    ECP5 Versa Development Kit

    Evaluate and develop for key connectivity features of the ECP5 FPGA, including PCI Express, Gigabit Ethernet, DDR3 and generic SERDES, includes numerous demos.
    ECP5 Versa Development Kit
  • ECP5-5G Versa Development Kit

    Board

    ECP5-5G Versa Development Kit

    Evaluate and develop for key connectivity features of the ECP5-5G FPGA, including PCI Express, Gigabit Ethernet, DDR3 and 5G SERDES, includes numerous demos.
  • FFT Compiler

    IP Core

    FFT Compiler

    Can be configured to perform forward FFT, inverse FFT (IFFT) or port selectable forward/inverse FFT. High-performance streaming and low-resource burst modes.
    FFT Compiler
  • SGMII and Gb Ethernet PCS

    IP Core

    SGMII and Gb Ethernet PCS

    Implements the PCS functions of both the Cisco SGMII and the IEEE 802.3z (1000BaseX) specifications
    SGMII and Gb Ethernet PCS
  • XAUI 10Gb Ethernet Attachment Unit Interface

    IP Core

    XAUI 10Gb Ethernet Attachment Unit Interface

    A complete configurable XAUI-to-XGMII solution. Implements 10Gb Ethernet (XGXS - IEEE 802.3ae-2002) and SERES-based PCS.
    XAUI 10Gb Ethernet Attachment Unit Interface
  • Crest Factor Reduction IP

    IP Core

    Crest Factor Reduction IP

    Reduces the peak-to-average ratio (PAR) of wideband digital signals. Highly configurable - up to 4 antennas with a wide variety of singal processing options.
    Crest Factor Reduction IP
  • Common Public Radio Interface - IP Core

    IP Core

    Common Public Radio Interface - IP Core

    Implements the physical layer of the CPRI specification (basic function) and link delay accuracy (low latency character).
    Common Public Radio Interface - IP Core
  • Cyclic Redundancy Check

    Reference Design

    Cyclic Redundancy Check

    Implements CRC generator and checker with polynomial orders from CRC-1 to CRC-64
    Cyclic Redundancy Check
  • 2D FIR Filter

    IP Core

    2D FIR Filter

    Performs real-time 2D convolution of windowed portions of incoming video frames with coefficient matrices held in internal memory
    2D FIR Filter
  • 8-bit Correlator

    IP Core

    8-bit Correlator

    Correlates an incoming data stream to a stored binary pattern called a code / coefficient sequence. Configure to 8 bit width, 256 channels, 2048 taps and more.
    8-bit Correlator
  • JESD207 IP

    IP Core

    JESD207 IP

    Implements baseband (BB) side data and control plane paths to connect to a radio front-end (RF) transceiver device with integrated ADC and DAC.
    JESD207 IP
  • Distributed Arithmetic FIR Filter Generator

    IP Core

    Distributed Arithmetic FIR Filter Generator

    Implements a highly configurable, multi-channel DA-FIR filter, using distributed arithmetic algorithms
    Distributed Arithmetic FIR Filter Generator
  • Turbo Decoder

    IP Core

    Turbo Decoder

    Flexible and compliant with 3GPP and CCSDS
    Turbo Decoder
  • Turbo Encoder

    IP Core

    Turbo Encoder

    Flexible and compliant with 3GPP, 3GPP2 and CCSDS
    Turbo Encoder
  • Block Convolutional Encoder

    IP Core

    Block Convolutional Encoder

    Parameterizable core for convolutional encoding of continuous or burst input data streams
    Block Convolutional Encoder
  • Block Viterbi Decoder

    IP Core

    Block Viterbi Decoder

    Parameterizable decoding different combinations of convolutionally encoded sequences.
    Block Viterbi Decoder
  • Cascaded Integrator-Comb (CIC) Filter

    IP Core

    Cascaded Integrator-Comb (CIC) Filter

    Widely parameterizable CIC filter that supports multiple channels with run-time programmable rates and differential delay parameters (aka Hogenauer Filter).
    Cascaded Integrator-Comb (CIC) Filter
  • Serial Rapid IO 2.1 Endpoint IP Core

    IP Core

    Serial Rapid IO 2.1 Endpoint IP Core

    Compliant with SRIO Rev. 2.1 specification. Up to 3.125Gbps in 1x, 2x and 4x lane configurations. 64-bit internal data paths.
    Serial Rapid IO 2.1 Endpoint IP Core
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