Lattice Solutions

IP Core

FFT Compiler IP Core

The FFT Compiler IP Core can be configured to perform forward FFT, inverse FFT (IFFT), or port selectable forward/inverse FFT.

ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M, LatticeXP2, Certus-NX, CertusPro-NX, MachXO5-NX, CrossLink-NX, Avant-E, Avant-G, Avant-X 

Data Communication, DSP, Guidance Systems, Automotive, DSP Bundle, SDR 

IP Core

USB 2.0 Device with FIFO Interface (USB20HF)

USB20HF IP Core provides FIFO & ULPI interface. It supports High Speed and Full Speed functionality for 15 IN/OUT endpoints.

CrossLink-NX, iCE40 UltraPlus, MachXO2 

FMC, Data Communication, Camera, ULPI, USB2, FIFO 

IP Core

5G O-RU L-PHY & H-PHY IP Cores

​​Yongatek's L-PHY IP in Lattice CertusPro-NX FPGA: 3GPP TS38.212 Release 16 compatible, O-RAN Alliance compliant, up to 6GHz, ideal for mid-power RF apps.​

CertusPro-NX 

CFR, CPRI, CRC, Data Communication, Data Compression, DSP, DUC, IEEE1588, AXI, SPI 

IP Core

Tri-Speed Ethernet MAC IP Core

The TSEMAC IP core have the logic, interfacing & clocking infra to ably integrate an external industry-standard Ethernet PHY with an internal processor

ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M, LatticeXP2, LatticeSC/M, CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX, Avant-E, Avant-G, Avant-X 

Data Communication, Ethernet, Defense, Automotive, APB, AXI, AXI-Lite Interface, AHB, Ethernet Bundle 

Board

KONDOR AX Development Board

ECP5 board for system design of HetNet, Industrial IoT, Cameras and Display applications

ECP5 / ECP5-5G 

ARM, CPRI, CSI-2, Data Communication, DDR SDRAM, Fiberoptic, FMC, HDMI, LVDS Video, MIPI, PCIe, SD Memory, SERDES, Soft Processor 

Board

ECP5 Versa Development Kit

Evaluate and develop for key connectivity features of the ECP5 FPGA, including PCI Express, Gigabit Ethernet, DDR3 and generic SERDES, includes numerous demos.

ECP5 / ECP5-5G 

Data Communication, Ethernet, PCIe, SERDES, SMA, Versa Connector, DDR SDRAM, TOR Switch, Guidance Systems 

Board

ECP5-5G Versa Development Kit

Evaluate and develop for key connectivity features of the ECP5-5G FPGA, including PCI Express, Gigabit Ethernet, DDR3 and 5G SERDES, includes numerous demos.

ECP5 / ECP5-5G 

Data Communication, Ethernet, PCIe, SERDES, SMA, Versa Connector, DDR SDRAM, Guidance Systems 

IP Core

SGMII and Gb Ethernet PCS IP Core

SGMII and Gb Ethernet PCS IP core is used as an interface for a discrete Ethernet PHY chip & can be used in bridging applications and/or PHY implementation.

ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M, CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX, Avant-E, Avant-G, Avant-X 

Data Communication, Ethernet, X/S/RGMII, Automotive, Ethernet Bundle 

IP Core

Time Sensitive Networking (TSN) End Node

The Time Sensitive Networking (TSN) End Node IP supports scheduling, priority queues, credit shaping, cyclic forwarding and preemption.

Certus-NX, CertusPro-NX, ECP5 / ECP5-5G 

IEEE1588, IEEE802.1, Data Communication, Ethernet, IEEE 802.3, AXI, TSN 

IP Core

Time Sensitive Networking (TSN) Network Node

Time Sensitive Networking (TSN) Switched End Node IP supports 3 Ports, scheduling, priority queues, credit shaping, redundancy, cyclic forwarding and preemption

Certus-NX, CertusPro-NX, ECP5 / ECP5-5G 

IEEE1588, IEEE802.1, Data Communication, Ethernet, IEEE 802.3, AXI, TSN 

IP Core

1G/10G TCP/IP Hardware Stack

Complete and scalable 1G/10G TCP/UDP/IP Hardware Stack.

CertusPro-NX, CrossLink-NX, Avant-E 

Data Communication, Ethernet, Internet Protocol 

IP Core

XAUI 10Gb Ethernet Attachment Unit Interface IP Core

10Gb Ethernet Attachment Unit Interface or XAUI includes support for the XAUI which is used to interface with physical layer devices in 10GbE networks.

ECP5 / ECP5-5G, LatticeECP3, LatticeECP2/M, CertusPro-NX 

Data Communication, Ethernet, X/S/RGMII, XAUI, Defense 

IP Core

Common Public Radio Interface - IP Core

Implements the physical layer of the CPRI specification (basic function) and link delay accuracy (low latency character).

LatticeECP3, LatticeSC/M, LatticeECP2/M, ECP5 / ECP5-5G 

CPRI, Data Communication 

Reference Design

Cyclic Redundancy Check Reference Design

Implements CRC generator and checker with polynomial orders from CRC-1 to CRC-64

MachXO2, MachXO 

CRC, Data Communication, Defense 

IP Core

2D FIR Filter

Performs real-time 2D convolution of windowed portions of incoming video frames with coefficient matrices held in internal memory

LatticeECP3, LatticeECP2/M, LatticeXP2 

Data Communication, DSP, Image Processing 

IP Core

8-bit Correlator

Correlates an incoming data stream to a stored binary pattern called a code / coefficient sequence. Configure to 8 bit width, 256 channels, 2048 taps and more.

LatticeECP2/M, LatticeSC/M, LatticeXP2 

Data Communication, DSP 

IP Core

Crest Factor Reduction IP

Reduces the peak-to-average ratio (PAR) of wideband digital signals. Highly configurable - up to 4 antennas with a wide variety of singal processing options.

ECP5 / ECP5-5G, LatticeECP3 

CFR, Data Communication, Defense, SDR 

IP Core

JESD207 IP

Implements baseband (BB) side data and control plane paths to connect to a radio front-end (RF) transceiver device with integrated ADC and DAC.

LatticeECP3 

ADC/DAC, CFR, CPRI, Data Communication, DSP, DUC 

IP Core

Distributed Arithmetic FIR Filter Generator

Implements a highly configurable, multi-channel DA-FIR filter, using distributed arithmetic algorithms

LatticeECP3, LatticeECP2/M, LatticeXP2 

Data Communication, DSP, Defense 

IP Core

Turbo Decoder

Flexible and compliant with 3GPP and CCSDS

LatticeECP2/M, LatticeXP2, LatticeECP3 

Data CODEC, Data Communication