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  • 5G O-RU L-PHY & H-PHY IP Cores

    IP Core

    5G O-RU L-PHY & H-PHY IP Cores

    ​​Yongatek's L-PHY IP in Lattice CertusPro-NX FPGA: 3GPP TS38.212 Release 16 compatible, O-RAN Alliance compliant, up to 6GHz, ideal for mid-power RF apps.​
    5G O-RU L-PHY & H-PHY IP Cores
  • KONDOR AX Development Board

    Board

    KONDOR AX Development Board

    ECP5 board for system design of HetNet, Industrial IoT, Cameras and Display applications
    KONDOR AX Development Board
  • Common Public Radio Interface - IP Core

    IP Core

    Common Public Radio Interface - IP Core

    Implements the physical layer of the CPRI specification (basic function) and link delay accuracy (low latency character).
    Common Public Radio Interface - IP Core
  • Digital Front End (DFE) Demo

    Demo

    Digital Front End (DFE) Demo

    Lattice DFE (Digital Front End) demonstration utilizing of CPRI (Common Public Radio Interface), DUC (Digital Up Converter) and CFR (Crest Factor Reduction).
    Digital Front End (DFE) Demo
  • JESD207 IP

    IP Core

    JESD207 IP

    Implements baseband (BB) side data and control plane paths to connect to a radio front-end (RF) transceiver device with integrated ADC and DAC.
    JESD207 IP
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