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  • eUSB 3.1 FMC

    Board

    eUSB 3.1 FMC

    eUSB 3.1 FMC board is to validate USB 3.1 functionality with FPGA’s inbuilt serial transceivers. It has ULPI PHY chip to validate USB 2.0 functionality.
    eUSB 3.1 FMC
  • 5G O-RU L-PHY & H-PHY IP Cores

    IP Core

    5G O-RU L-PHY & H-PHY IP Cores

    ​​Yongatek's L-PHY IP in Lattice CertusPro-NX FPGA: 3GPP TS38.212 Release 16 compatible, O-RAN Alliance compliant, up to 6GHz, ideal for mid-power RF apps.​
    5G O-RU L-PHY & H-PHY IP Cores
  • FlinQ – Flawless Link Quality Encoder / Decoder IP-cores

    IP Core

    FlinQ – Flawless Link Quality Encoder / Decoder IP-cores

    FlinQ™ enables higher quality and a significant gain of efficiency for high performance and reliable visual communication over both wired and wireless links.
    FlinQ – Flawless Link Quality Encoder / Decoder IP-cores
  • TICO-RAW Encoder/Decoder IP-cores

    IP Core

    TICO-RAW Encoder/Decoder IP-cores

    TICO-RAW is a revolutionary RAW compression, extremely tiny & low power, with low latency and lossless quality to handle camera and sensor data (Bayer).
    TICO-RAW Encoder/Decoder IP-cores
  • ​​I3C-SC: MIPI I3C Basic Secondary Controller​

    IP Core

    ​​I3C-SC: MIPI I3C Basic Secondary Controller​

    ​​Highly featured I3C Basic Secondary Controller (Controller-Capable Slave). Optional I3C-to-AHB bridge functionality from over-I3C remote access of local AHB bus. Works to any Lattice FPGA device.​
    ​​I3C-SC: MIPI I3C Basic Secondary Controller​
  • ZipAccel-C: GZIP/ZLIB/Deflate Data Compression

    IP Core

    ZipAccel-C: GZIP/ZLIB/Deflate Data Compression

    ZipAccel-C: GZIP/ZLIB/Deflate Compression Core is a custom hardware implementation of a lossless data compression engine that complies with the Deflate, GZIP, and ZLIB compression standards.
    ZipAccel-C: GZIP/ZLIB/Deflate Data Compression
  • ZipAccel-D: GUNZIP/ZLIB/Inflate Data Decompression

    IP Core

    ZipAccel-D: GUNZIP/ZLIB/Inflate Data Decompression

    ZipAccel-D: Decompression engine for GZIP/ZLIB/Deflate files is a custom hardware implementation of a lossless data decompression engine that complies with the Inflate/Deflate, GZIP/GUNZIP, and ZLIB compression standards.
    ZipAccel-D: GUNZIP/ZLIB/Inflate Data Decompression
  • JPEG-DX-F - Ultra-Fast Baseline and Extended JPEG Decoder

    IP Core

    JPEG-DX-F - Ultra-Fast Baseline and Extended JPEG Decoder

    Scalable, ultra-high throughput 8/12-bit JPEG decoder. Ideal for low-latency motion-Jpeg streaming. Full-HD or Ultra-HD capable depending on the device.
    JPEG-DX-F - Ultra-Fast Baseline and Extended JPEG Decoder
  • JPEG-DX-S - Baseline and Extended JPEG Decoder

    IP Core

    JPEG-DX-S - Baseline and Extended JPEG Decoder

    Compact, 8bit and 12bit per color, JPEG decoder. Ideal for low-latency motion-Jpeg streaming.
    JPEG-DX-S - Baseline and Extended JPEG Decoder
  • JPEG-EX-F - Ultra-Fast Baseline and Extended JPEG Encoder

    IP Core

    JPEG-EX-F - Ultra-Fast Baseline and Extended JPEG Encoder

    Scalable, ultra-high throughput 8/12-bit encoder. Highly configurable with advanced bit-rate control. Ideal for low-latency motion-Jpeg streaming.
    JPEG-EX-F - Ultra-Fast Baseline and Extended JPEG Encoder
  • JPEG-EX-S - Baseline and Extended JPEG Encoder

    IP Core

    JPEG-EX-S - Baseline and Extended JPEG Encoder

    Compact, 8bit and 12bit per color, JPEG encoder. Highly configurable with advanced bit-rate control features. Ideal for low-latency motion-Jpeg streaming.
    JPEG-EX-S - Baseline and Extended JPEG Encoder
  • PNG Lossless Compression Decoder

    IP Core

    PNG Lossless Compression Decoder

    Compact and fast PNG compression decoder with streaming input and output interfaces.
    PNG Lossless Compression Decoder
  • Tri-Rate Serial Digital Interface Physical Layer

    IP Core

    Tri-Rate Serial Digital Interface Physical Layer

    A complete SDI PHY SERDES-based interface bridging high-speed SDI serial data to formatted parallel video data. Compliant to numerous SMPTE standards.
    Tri-Rate Serial Digital Interface Physical Layer
  • LZRW3 Data Compression Core

    IP Core

    LZRW3 Data Compression Core

    Implements the LZRW3 data compression algorithm in FPGA without the need for external memory storage. Capable of over 1 Gigabit/sec.
    LZRW3 Data Compression Core
  • Payload Compression System

    IP Core

    Payload Compression System

    Uses a very robust and mature implementation of the LZRW lossless compression algorithm
    Payload Compression System
  • LT-125 Video Codec Evaluation Platform

    Board

    LT-125 Video Codec Evaluation Platform

    A LatticeECP3 based HD video compression and decompression evaluation platform
    LT-125 Video Codec Evaluation Platform
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