Tri-Rate Serial Digital Interface Physical Layer

Serial Digital Interface (SDI) is the most popular raw video connectivity standard used in television broadcast studios and video production facilities. The availability of high-speed serial inputs/outputs and general purpose programmable logic makes FPGAs (field programmable gate arrays) ideal devices to be used for acquisition, mixing, storage, editing, processing and format conversion applications. Simpler applications use FPGAs to acquire SDI data from one or more SD (standard definition), HD (high definition) or 3G (3-Gigabit HD) sources, perform simple processing and re-transmit the video data in SDI format. Such applications require an SDI PHY (physical layer) interface and some basic processing blocks like a color space converter. In more complex applications, the acquired video is taken through multiple processing phases, like de-interlacing, video format conversion, filtering, scaling, graphics mixing and picture-in-picture display. FPGA devices can also be used as a bridge between SDI video sources and backplane protocols such as PCI Express or Ethernet, with or without any additional video processing.

Lattice's Tri-Rate SDI PHY IP (intellectual property) core is a complete SDI PHY interface that connects to the high-speed SDI serial data on one side (through LatticeECP3™ SERDES) and the formatted parallel video data on the other side. It enables faster development of applications for processing, storing, and bridging SDI video data. It is comprised of the following major functional blocks: SDI encoder/decoder, word alignment, CRC detection and checking, VPID (video payload identifier) insertion and extraction, and rate detection logic. The IP core supports the following interface standards and source formats for SDI as specified in standards published by the Society for Motion Picture and Television Engineers (SMPTE).

  • Interface: SMPTE 259M-2006 [1] (SD), SMPTE 292M-1998 [2] (HD) and SMPTE 424 M [3] (3G)
  • SD source formats: SMPTE 125M [4] and SMPTE 267M [5] (13.5 Mhz only)
  • HD source formats: SMPTE 260M [6], SMPTE 274M [7], SMPTE 295M [8] and SMPTE 296M [9]
  • 3G source formats: SMPTE 425M [10]

The IP, when connected with the LatticeECP3 SERDES, can transmit and/or receive any of the supported video standards and formats through a common physical serial interface. The IP core can automatically scan and lock on to any of the supported video streams. Receiving multiple standards requires appropriate external clocks to be supplied by the application in response to commands from the IP core.


  • Dynamic reception of multiple interface standards over the same physical cable: SD-SDI, HD-SDI and 3G-SDI interfaces
  • Automatic Rx (receive) rate detection and dynamic Tx (transmit) rate selection
  • Multiple SD source formats support: SMPTE 125M [4] and SMPTE 267M [5] (13.5 MHz only)
  • Multiple HD source formats support: SMPTE 260M [6], SMPTE 274M [7], SMPTE 295M [8] and SMPTE 296M [9]
  • Support for 3G source formats, including 3G Level-B format: SMPTE 425M [10]
  • Word alignment and timing reference sequence (TRS) detection
  • Field, vertical blanking (vblank) and horizontal blanking (hblank) timing signals generation
  • CRC computation, error checking and insertion for HD/3GLine number (LN) decoding and encoding for HD/3G
  • Custom source format support for HD/3G
  • Video Payload Identifier (VPID) insertion and extraction for HD/3G
  • 10-bit parallel input/output support for SD
  • Soft-logic based low data-rate (LDR) serializer for SD transmission

Jump to

Block Diagram

Tri-Rate Serial Digital Interface (SDI) Physical Layer (PHY) IP Core Block Diagram

Performance and Size

IP Express User Configurable Mode SLICEs LUTs Registers TxClock RxClock
1 - PHY function=Tx/Rx, Enable 3G level B=Yes, VPID insertion=On 1306 2506 1795 181 150
2 - PHY function=Tx/Rx, Enable 3G level B=Yes, VPID insertion=Off 918 1747 1283 248 176
3 - PHY function=Tx/Rx, Enable 3G level B=No, VPID insertion=On 926 1772 1243 185 178
4 - PHY function=Tx/Rx, Enable 3G level B=No, VPID insertion=Off 733 1403 1009 285 149
5 - PHY function=Tx, Enable 3G level B=Yes, VPID insertion=On 436 845 491 182 -
6 - PHY function=Rx, Enable 3G level B=Yes 905 1714 1321 - 164

1. Performance and utilization data are generated using an LFE3-95E-7FN1156CES device with Lattice Diamond 1.3 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family.

Ordering Information

  Part Number
Device Family Multi-Site Perpetual Single Seat Annual

IP Version: 1.3

Evaluate: To download a full evaluation version of this IP, go to the IPexpress tool and click the IP Server button in the toolbar. All LatticeCORE IP cores and modules available for download will be visible. For more information on viewing/downloading IP please read the IP Express Quick Start Guide.

Purchase: To find out how to purchase the IP Core, please contact your local Lattice Sales Office.


Quick Reference
Select All
Tri-Rate SDI PHY IP Loopback and Passthrough Sample Designs
UG22 1.1 10/30/2009 PDF 222.2 KB
Tri-Rate SDI PHY IP Core
IPUG82 01.5 1/17/2011 PDF 1.2 MB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.