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  • TICO-RAW Encoder/Decoder IP-cores

    IP Core

    TICO-RAW Encoder/Decoder IP-cores

    TICO-RAW is a revolutionary RAW compression, extremely tiny & low power, with low latency and lossless quality to handle camera and sensor data (Bayer).
    TICO-RAW Encoder/Decoder IP-cores
  • Turbo Decoder

    IP Core

    Turbo Decoder

    Flexible and compliant with 3GPP and CCSDS
    Turbo Decoder
  • Turbo Encoder

    IP Core

    Turbo Encoder

    Flexible and compliant with 3GPP, 3GPP2 and CCSDS
    Turbo Encoder
  • Block Convolutional Encoder

    IP Core

    Block Convolutional Encoder

    Parameterizable core for convolutional encoding of continuous or burst input data streams
    Block Convolutional Encoder
  • Block Viterbi Decoder

    IP Core

    Block Viterbi Decoder

    Archived IP Core supporting LatticeECP2/M, LatticeXP2 and LatticeECP3 FPGAs - For reference only
    Block Viterbi Decoder
  • 8b/10b Encoder/Decoder

    Reference Design

  • Dynamic Block Reed-Solomon Decoder

    IP Core

    Dynamic Block Reed-Solomon Decoder

    Highly configurable, and compliant with several industry standards including IEEE 802.16-2004
    Dynamic Block Reed-Solomon Decoder
  • Dynamic Block Reed-Solomon Encoder

    IP Core

    Dynamic Block Reed-Solomon Encoder

    Used to perform Forward Error Correction (FEC) in data communications and digital video broadcasting. Highly configurable.
    Dynamic Block Reed-Solomon Encoder
  • ECC Module Reference Design

    Reference Design

    ECC Module Reference Design

    Provides Single Error Correction - Double Error Detection (SECDED) capability based on a class of optimal minimum oddweight error parity codes
    ECC Module Reference Design
  • Common Scrambling Algorithm Cores

    IP Core

    Common Scrambling Algorithm Cores

    Implement the ETSI specified Common Scrambling Algorithm (CSA) which is used to provide the conditional access mechanism for MPEG-2 video streams
    Common Scrambling Algorithm Cores
  • Fast AES Core

    IP Core

    Fast AES Core

    Implements AES (Rijndael) to latest NIST FIPS PUB 197. Full dynamic support for all AES key sizes (128, 192 and 256-bits)
    Fast AES Core
  • Fast Hash Core

    IP Core

    Fast Hash Core

    Implements the NIST approved SHA-1, SHA-224, SHA-256, SHA-384 and SHA-512 secure hash algorithms to FIPS 180-3 and the legacy MD5 hash algorithm to RFC 1321
    Fast Hash Core
  • LZRW3 Data Compression Core

    IP Core

    LZRW3 Data Compression Core

    Implements the LZRW3 data compression algorithm in FPGA without the need for external memory storage. Capable of over 1 Gigabit/sec.
    LZRW3 Data Compression Core
  • TC1000-WiMAX: 802.16 d/e CTC

    IP Core

    TC1000-WiMAX: 802.16 d/e CTC

    Convolutional Turbo Code (CTC) decoder optimized for IEEE 802.16 d/e applications
    TC1000-WiMAX: 802.16 d/e CTC
  • TC1700: Turbo decoder Core for HSPA+, LTE & WiMAX

    IP Core

    TC1700: Turbo decoder Core for HSPA+, LTE & WiMAX

    Turbo decoder supporting three PHY layer specifications - 3GPP-HSPA, 3GPP-LTE, WiMAX IEEE802.16e
    TC1700: Turbo decoder Core for HSPA+, LTE & WiMAX
  • TC4400: ITU-Ghn LDPC Encoder/Decoder Cores

    IP Core

    TC4400: ITU-Ghn LDPC Encoder/Decoder Cores

    LDPC decoder Core fully compliant with ITU-Ghn (wireline home networking) specifications
    TC4400: ITU-Ghn LDPC Encoder/Decoder Cores
  • TC7000-LTE: 3GPP-Long Term Evolution CTC Decoder

    IP Core

    TC7000-LTE: 3GPP-Long Term Evolution CTC Decoder

    Convolutional turbo code (CTC) decoder optimized for 3GPP/LTE specifications
    TC7000-LTE: 3GPP-Long Term Evolution CTC Decoder
  • GRSPW_CODEC SpaceWire Codec IP Core

    IP Core

    GRSPW_CODEC SpaceWire Codec IP Core

    The GRSPW_CODEC core implements a SpaceWire encoder decoder with a 9-bit wide FIFO host interface in each direction. The core complies to the SpaceWire standard (ECSS-E-ST-12C). Data is transmitted and received through FIFOs with configurable depth.
    GRSPW_CODEC SpaceWire Codec IP Core
  • 1553 Encoder/Decoder

    Reference Design

    1553 Encoder/Decoder

    Implements Manchester II encoding and decoding required by the 1553 along with synchronization pattern insertion and identification.
     
    1553 Encoder/Decoder
  • Parallel FIR Filter

    IP Core

    Parallel FIR Filter

    Archived IP Core supporting ORCA FPGAs - For reference only.
     
    Parallel FIR Filter
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