Lattice Solutions

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  • BSCAN - Multiple Port Linker (BSCAN2)

    Reference Design

    BSCAN - Multiple Port Linker (BSCAN2)

    Implements an IEEE 1149.1 compliant Boundary Scan port on an FPGA. Multiple scan ports are linked together feeing into the IEEE 1149.1 port.
    BSCAN - Multiple Port Linker (BSCAN2)
  • BSCAN - Multiple Port Addressable Buffer (BSCAN-1)

    Reference Design

    BSCAN - Multiple Port Addressable Buffer (BSCAN-1)

    A multiple boundary scan test access port (TAP) addressable buffer function that can be accessed through a standard IEEE 1149.1 interface
    BSCAN - Multiple Port Addressable Buffer (BSCAN-1)
  • ispMACH 4256V Breakout Board

    Board

    ispMACH 4256V Breakout Board

    A simple low-cost board that provides complete I/O access to the ispMACH4256V (TN144 package)+LEDs, Prototyping area and more.
    ispMACH 4256V Breakout Board
  • 8b/10b Encoder/Decoder

    Reference Design

  • Power Manager II Fault Logger

    Reference Design

    Power Manager II Fault Logger

    Records the supply fault condition in non-volatile memory so the fault(s) can read back at some later time
    Power Manager II Fault Logger
  • HDLC Controller

    Reference Design

    HDLC Controller

    Implements HDLC (High-Level Data Link Control), located at the OSI link layer 2. supports LAPB, LAPD, LLC and SDLC with a few modifications
    HDLC Controller
  • PWM Fan Controller - WISHBONE Compatible

    Reference Design

    PWM Fan Controller - WISHBONE Compatible

    Implements a PWM fan control using a PLD and a MOSFET circuit to provide the speed control of a simple 2-pin or 3-pin fan.
    PWM Fan Controller - WISHBONE Compatible
  • Arbitration and Switching Between Bus Masters

    Reference Design

    Arbitration and Switching Between Bus Masters

    Provides a mode of connection and arbitration between multiple bus masters. While an I2C bus is used in this design, it is applicable to other protocols.
    Arbitration and Switching Between Bus Masters
  • Standard SDRAM Controller for ispMACH Devices

    Reference Design

    Standard SDRAM Controller for ispMACH Devices

    SDRAM Interface to standard microprocessors, independent of the processor type. The design as shown supports two 16MB memory regions configured as 4 M x 32 bits
    Standard SDRAM Controller for ispMACH Devices
  • ispMACH4064Z Evaluation Board

    Board

    ispMACH4064Z Evaluation Board

    Evaluation board for the ispMACH4064ZC + LCD panel + Power from 9V battery, AC adapter, or banana jack inputs.
    ispMACH4064Z Evaluation Board
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