Lattice Solutions

IP Core

Timer/Counter IP Core

The Lattice Semiconductor Timer/Counter IP is used to track timeouts in the system, and it generates an interrupt to the CPU when a timeout is detected.

Certus-NX, CrossLink-NX, Avant-E, Avant-G, Avant-X, CertusPro-NX, CrossLink, CrossLinkPlus, ECP5 / ECP5-5G, iCE40 LP/HX, iCE40 Ultra / UltraLite, iCE40 UltraPlus, LatticeECP2/M, LatticeECP3, LatticeSC/M, LatticeXP2, Mach-NX, MachXO, MachXO2, MachXO3, MachXO3D, MachXO5-NX 

AMBA, Lattice Propel, Lattice Diamond, Lattice Radiant, APB, AHB-Lite, Lattice Sentry, Lattice Sentry PFR IP Package, Security 

IP Core

Helion IONOS Image Signal Processing IP Portfolio

Comprehensive, high-quality, highly-configurable ISP solution from Helion Vision, from basic to advanced High Dynamic Range Imaging (HDRI) color pipelines.

MachXO, LatticeXP2, LatticeECP3, CrossLink, ECP5 / ECP5-5G, CrossLink-NX 

HDR, Image Processing, Video Tx/Rx, Lattice mVision, Automotive 

Reference Design

I2C Bus Master

Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device

MachXO, LatticeXP2, ispMACH 4000ZE, MachXO2, LatticeECP3, Platform Manager, ECP5 / ECP5-5G, MachXO3 

Bus Controllers, I2C, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, 5G 

Reference Design

I2C Master - WISHBONE Compatible

Based on the OpenCores I2C master core, this Reference Design provides a bridge between the I2C and WISHBONE bus

MachXO, MachXO2, LatticeXP2, LatticeECP3, ECP5 / ECP5-5G, MachXO3 

I2C, Wishbone, Bus Controllers, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, 5G 

Reference Design

Simple Sigma-Delta ADC

Implements an Analog-to-Digital (ADC) using on-FPGA differntial LVDS inputs (or inexpensive analog comparitor). Save cost by eliminating external ADC devices.

MachXO, MachXO2, LatticeXP2, iCE40 UltraPlus 

ADC/DAC, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Guidance Systems 

Reference Design

UART Reference Design

The UART reference design describes a fully configurable UART optimized for and implemented in a variety of Lattice devices.

ispMACH 4000ZE, MachXO, LatticeXP2, Platform Manager, MachXO5-NX, MachXO2 

Bus Controllers, UART 

Reference Design

UART Reference Design - WISHBONE Compatible

UART (Universal Asynchronous Receiver/Transmitter) provides both Rx and Tx between the WISHBONE system bus and an RS232 serial communication channel.

MachXO, LatticeXP2, MachXO2, MachXO3 

Bus Controllers, UART, Wishbone, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, 5G 

Reference Design

SDR SDRAM Controller-Advanced Reference Design

Provides a simple generic system interface to the bus master, reducing the user's effort to deal with the SDRAM command interface.

MachXO, ispMACH 4000ZE, LatticeXP2, MachXO2, LatticeECP3, ECP5 / ECP5-5G, MachXO3 

DDR SDRAM 

Reference Design

SD Flash Controller Using SD Bus

MachXO, MachXO2, LatticeECP3, ECP5 / ECP5-5G, MachXO3 

SD Memory, Wishbone 

Reference Design

Cyclic Redundancy Check Reference Design

Implements CRC generator and checker with polynomial orders from CRC-1 to CRC-64

MachXO2, MachXO 

CRC, Data Communication, Defense 

Reference Design

BSCAN - Multiple Port Linker (BSCAN2)

Implements an IEEE 1149.1 compliant Boundary Scan port on an FPGA. Multiple scan ports are linked together feeing into the IEEE 1149.1 port.

MachXO, MachXO2, ispMACH 4000ZE, ispMACH 4000V/B/C/Z, LatticeXP2, ECP5 / ECP5-5G 

IEEE 1149.1, Boundary Scan 

Reference Design

I2C Bus Controller for Serial EEPROMs

Provides an interface between standard microprocessors and I2C Serial EEPROM devices

MachXO, LatticeXP2, ispMACH 4000ZE, MachXO2, LatticeECP3, ECP5 / ECP5-5G, MachXO3 

Bus Controllers, I2C 

Reference Design

I2C Slave/Peripheral

Implements an I2C slave module in a FPGA or CPLD. Follows the I2C specification to provide device addressing, read/write operation and acknowledgment

LatticeECP3, LatticeXP2, MachXO, Platform Manager, ispMACH 4000ZE, ECP5 / ECP5-5G 

I2C, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets 

Reference Design

LED/OLED Driver Reference Design

Drive an LED via WISHBONE bus. Default is targeted to a GM1WA55311A LED but can be used to control other LEDs or OLEDs with similar functions.

MachXO, MachXO2, MachXO3 

LED Control, Wishbone, UAVs 

Reference Design

SPI Controller - WISHBONE Compatible

Provides an interface between a microprocessor with a WISHBONE bus and external SPI devices.

ispMACH 4000ZE, MachXO, LatticeXP2, MachXO2, MachXO3 

SPI, Wishbone, TOR Switch 

Reference Design

Single-Wire Controller for Digital Temp. Sensors

Implements a Single Wire controller connected to a WISHBONE bus. Provides an example communicating to a Temperature Sensor.

MachXO, MachXO2 

Single Wire, Temperature Sensor, Wishbone 

Reference Design

I2S Controller with WISHBONE Interface

Implements an I2S transmit master or I2S receive master with a WISHBONE interface

MachXO, MachXO2, MachXO3 

Bus Controllers, I2S, Wishbone, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets 

Reference Design

NOR Flash Memory Controller - WISHBONE Compatible

Provides a NOR flash memory controller through WISHBONE bus. It supports several common operational modes of a NOR flash

MachXO, MachXO2 

NOR Flash, Wishbone, Defense 

Reference Design

LPC (Low Pin Count) Bus Controller

Implements a Low Pin Count bus controller - based on the Intel Low Pin Count Interface Specification (version 1.1)

MachXO2, LatticeXP2, LatticeECP3, ispMACH 4000ZE, MachXO 

Bus Controllers, LPC, Signal Aggregation, TOR Switch 

Reference Design

I2C Slave to SPI Master Bridge

Implements an I2C slave to SPI master bridge.

MachXO, Platform Manager 

I2C, SPI, TOR Switch