Device Family |
Tested Devices* |
Performance |
I/O Pins |
Utilization |
Revision |
ECP5™ 7 |
LFE5U-45F-6MG285C |
>33MHz |
18 |
198 LUTs |
5.8 |
LatticeECP3™ 1 |
LFE3-17EA-6FTN256C |
>33MHz |
18 |
200 LUTs |
5.8 |
MachXO3L™ 8 |
LCMXO3L-4300C-6BG256C |
>33MHz |
18 |
204 LUTs(Verilog-LSE Source) |
5.8 |
190 LUTs (Verilog-Syn Source) |
5.8 |
200 LUTs (VHDL-LSE Source) |
5.8 |
191 LUTs (VHDL-Syn Source) |
5.8 |
MachXO2™ 2 |
LCMXO2-256HC-4TG100C |
>33MHz |
18 |
191 LUTs |
5.8 |
MachXO™ 3 |
LCMXO256C-3T100C |
>33MHz |
18 |
192 LUTs |
5.8 |
LatticeXP2™ 4 |
LFXP2-5E-5M132C |
>33MHz |
18 |
201 LUTs |
5.8 |
ispMACH® 4000ZE5 |
LC4256ZE-5TN144C |
>33MHz |
18 |
154 LUTs |
5.8 |
Platform Manager™ 6 |
LPTM10-1247-3TG128CES |
>33MHz |
18 |
192 LUTs |
5.8 |
* May work in other devices as well.
Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.