| Device Family |
Tested Devices* |
Performance |
I/O Pins |
Design Size |
Revision |
| MachXO3L™ 6 |
LCMXO3L-4300C-
6BG256C |
>50MHz |
29 |
201 LUTs(Verilog-LSE Source) |
1.5 |
| 243 LUTs (Verilog-Syn Source) |
1.5 |
| 218 LUTs (VHDL-LSE Source) |
1.5 |
| 243 LUTs (VHDL-Syn Source) |
1.5 |
| MachXO2™ 1 |
LCMXO2-1200HC-
4TG100C |
>50MHz |
29 |
201 LUTs (Verilog Source)
218 LUTs (VHDL Source) |
1.5 |
| MachXO™ 2 |
LCMXO256C-
3T100C |
>50MHz |
29 |
198 LUTs (Verilog Source)
217 LUTs (VHDL Source) |
1.5 |
| ECP5™ 5 |
LFE5U-45F-
6MG285C |
>50MHz |
29 |
203 LUTs (Verilog Source)
209 LUTs (VHDL Source) |
1.5 |
| LatticeECP3™ 3 |
LFE3-17EA-
6FTN256C |
>50MHz |
29 |
261 LUTs (Verilog Source)
252 LUTs (VHDL Source) |
1.5 |
| LatticeXP2™ 4 |
LFXP2-5E-
5M132C |
>50MHz |
29 |
252 LUTs (Verilog Source)
248 LUTs (VHDL Source) |
1.5 |
* May work in other devices as well.
Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.