莱迪思解决方案

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  • FIR 滤波器生成器

    IP Core

    FIR 滤波器生成器

    可灵活配置的多通道FIR滤波器。最多支持256个通道,每个拥有2048个抽头。输入和系数宽度为4至32位。
    FIR 滤波器生成器
  • Helion IONOS图像信号处理IP系列

    IP Core

    Helion IONOS图像信号处理IP系列

    来自Helion Vision的全面、高质量、可自行配置的ISP解决方案,包括了从基本到高级的高动态范围成像(HDRI)色彩流水线。
    Helion IONOS图像信号处理IP系列
  • 三倍速以太网MAC

    IP Core

    三倍速以太网MAC

    在主机处理器和以太网之间发送和接收数据。符合IEEE 802.3标准。支持10/100/1000 Mbps传输速率。
    三倍速以太网MAC
  • I2C (Inter-Integrated Circuit) 主控- WISHBONE兼容

    Reference Design

  • I2C总线主控

    Reference Design

    I2C总线主控

    Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device
    I2C总线主控
  • 色彩空间转换器

    IP Core

    色彩空间转换器

    免费IP核——支持颜色空间转换和相关的CODEC功能(数据宽度为8-16位、精度高达18位)。支持RGB、YCbCr、CMYK及更多格式之间的转换。
    色彩空间转换器
  • LatticeMico32开放、免费的32位软处理器

    IP Core

    LatticeMico32开放、免费的32位软处理器

    A 32-bit Harvard, RISC architecture soft microprocessor, available for free with an open IP core license. Many compatible modules and IP are available.
    LatticeMico32开放、免费的32位软处理器
  • CORDIC(坐标旋转数字计算机)

    IP Core

    CORDIC(坐标旋转数字计算机)

    The Lattice CORDIC IP uses full internal precision while allowing variable output precision with several choices for rounding.
    CORDIC(坐标旋转数字计算机)
  • Scatter-Gather 直接存储器访问(DMA)控制器

    IP Core

    Scatter-Gather 直接存储器访问(DMA)控制器

    通过scatter-gather功能实现可配置、多通道、符合WISHBONE规范的DMA控制器
    Scatter-Gather 直接存储器访问(DMA)控制器
  • HWD-XP2-USB by JK Hardware Design

    Board

    HWD-XP2-USB by JK Hardware Design

    General purpose evaluation and development platform for LatticeXP2
    HWD-XP2-USB by JK Hardware Design
  • 简单的Σ-Δ ADC

    Reference Design

    简单的Σ-Δ ADC

    Implements an Analog-to-Digital (ADC) using on-FPGA differntial LVDS inputs (or inexpensive analog comparitor). Save cost by eliminating external ADC devices.
    简单的Σ-Δ ADC
  • UART - WISHBONE兼容

    Reference Design

    UART - WISHBONE兼容

    UART (Universal Asynchronous Receiver/Transmitter) provides both Rx and Tx between the WISHBONE system bus and an RS232 serial communication channel.
    UART - WISHBONE兼容
  • 通用异步接收器/发送器

    Reference Design

    通用异步接收器/发送器

    UART参考设计描述了一个充分可配置的UART,针对各种莱迪思器件进行了优化和实现。
    通用异步接收器/发送器
  • SDR SDRAM 控制器 - 高级

    Reference Design

    SDR SDRAM 控制器 - 高级

    Provides a simple generic system interface to the bus master, reducing the user's effort to deal with the SDRAM command interface.
    SDR SDRAM 控制器 - 高级
  • 伽玛校正

    IP Core

    伽玛校正

    The Lattice Gamma Corrector IP core is a multi-color plane gamma correction system that can support almost any custom gamma correction requirement.
    伽玛校正
  • 2D图像缩放IP核

    IP Core

    2D图像缩放IP核

    Highly-configurable design to convert input video frames of one size to output video frames of a different size
    2D图像缩放IP核
  • BSCAN - 多端口连接器 (BSCAN2)

    Reference Design

    BSCAN - 多端口连接器 (BSCAN2)

    Implements an IEEE 1149.1 compliant Boundary Scan port on an FPGA. Multiple scan ports are linked together feeing into the IEEE 1149.1 port.
    BSCAN - 多端口连接器 (BSCAN2)
  • I2C从/外设

    Reference Design

    I2C从/外设

    Implements an I2C slave module in a FPGA or CPLD. Follows the I2C specification to provide device addressing, read/write operation and acknowledgment
    I2C从/外设
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