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  • Helion IONOS Image Signal Processing IP Portfolio

    IP Core

    Helion IONOS Image Signal Processing IP Portfolio

    Comprehensive, high-quality, highly-configurable ISP solution from Helion Vision, from basic to advanced High Dynamic Range Imaging (HDRI) color pipelines.
    Helion IONOS Image Signal Processing IP Portfolio
  • Tri-Speed Ethernet MAC IP Core

    IP Core

    Tri-Speed Ethernet MAC IP Core

    The TSEMAC IP core have the logic, interfacing & clocking infra to ably integrate an external industry-standard Ethernet PHY with an internal processor
    Tri-Speed Ethernet MAC IP Core
  • I2C Bus Master

    Reference Design

    I2C Bus Master

    Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device
    I2C Bus Master
  • I2C Master - WISHBONE Compatible

    Reference Design

    I2C Master - WISHBONE Compatible

    Based on the OpenCores I2C master core, this Reference Design provides a bridge between the I2C and WISHBONE bus
    I2C Master - WISHBONE Compatible
  • Color Space Converter (CSC) IP Core

    IP Core

    Color Space Converter (CSC) IP Core

    The Lattice Color Space Converter IP Core is widely parameterizable and can support any custom color space conversion requirement.
    Color Space Converter (CSC) IP Core
  • FFT Compiler IP Core

    IP Core

    FFT Compiler IP Core

    The FFT Compiler IP Core can be configured to perform forward FFT, inverse FFT (IFFT), or port selectable forward/inverse FFT.
    FFT Compiler IP Core
  • FIR Filter Generator IP Core

    IP Core

    FIR Filter Generator IP Core

    This IP core is a widely configurable, multi-channel FIR filter, implemented using high performance sysDSP™ blocks available in Lattice devices.
    FIR Filter Generator IP Core
  • LatticeMico32 Open, Free 32-Bit Soft Processor

    IP Core

    LatticeMico32 Open, Free 32-Bit Soft Processor

    A 32-bit Harvard, RISC architecture soft microprocessor, available for free with an open IP core license. Many compatible modules and IP are available.
    LatticeMico32 Open, Free 32-Bit Soft Processor
  • Coordinate Rotational Digital Computer (CORDIC) IP Core

    IP Core

    Coordinate Rotational Digital Computer (CORDIC) IP Core

    The Lattice CORDIC IP uses full internal precision while allowing variable output precision with several choices for rounding.
    Coordinate Rotational Digital Computer (CORDIC) IP Core
  • Scatter-Gather DMA Controller IP Core

    IP Core

    Scatter-Gather DMA Controller IP Core

    Implements a configurable, multi-channel, WISHBONE-compliant DMA controller with scatter-gather capability
    Scatter-Gather DMA Controller IP Core
  • Video Frame Buffer IP Core

    IP Core

    Video Frame Buffer IP Core

    The Video Frame Buffer IP core buffers video data in external memory to be displayed on output devices such as computer monitors, projectors, etc
    Video Frame Buffer IP Core
  • HWD-XP2-USB by JK Hardware Design

    Board

    HWD-XP2-USB by JK Hardware Design

    General purpose evaluation and development platform for LatticeXP2
    HWD-XP2-USB by JK Hardware Design
  • Simple Sigma-Delta ADC

    Reference Design

    Simple Sigma-Delta ADC

    Implements an Analog-to-Digital (ADC) using on-FPGA differntial LVDS inputs (or inexpensive analog comparitor). Save cost by eliminating external ADC devices.
    Simple Sigma-Delta ADC
  • UART Reference Design

    Reference Design

    UART Reference Design

    The UART reference design describes a fully configurable UART optimized for and implemented in a variety of Lattice devices.
    UART Reference Design
  • UART Reference Design - WISHBONE Compatible

    Reference Design

    UART Reference Design - WISHBONE Compatible

    UART (Universal Asynchronous Receiver/Transmitter) provides both Rx and Tx between the WISHBONE system bus and an RS232 serial communication channel.
    UART Reference Design - WISHBONE Compatible
  • Gamma Corrector IP Core

    IP Core

    Gamma Corrector IP Core

    The Lattice Gamma Corrector IP core is a multi-color plane gamma correction system that can support almost any custom gamma correction requirement.
    Gamma Corrector IP Core
  • SDR SDRAM Controller-Advanced Reference Design

    Reference Design

    SDR SDRAM Controller-Advanced Reference Design

    Provides a simple generic system interface to the bus master, reducing the user's effort to deal with the SDRAM command interface.
    SDR SDRAM Controller-Advanced Reference Design
  • 2D Scaler IP Core

    IP Core

    2D Scaler IP Core

    Highly-configurable design to convert input video frames of one size to output video frames of a different size
    2D Scaler IP Core
  • BSCAN - Multiple Port Linker (BSCAN2)

    Reference Design

    BSCAN - Multiple Port Linker (BSCAN2)

    Implements an IEEE 1149.1 compliant Boundary Scan port on an FPGA. Multiple scan ports are linked together feeing into the IEEE 1149.1 port.
    BSCAN - Multiple Port Linker (BSCAN2)
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