Lattice Solutions

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  • Tri-Speed Ethernet MAC Core IP

    IP Core

    Tri-Speed Ethernet MAC Core IP

    Transmits and receives data between a host processor and an Ethernet network. IEEE 802.3 compliant. Supports 10/100/1000 operation.
    Tri-Speed Ethernet MAC Core IP
  • I2C Bus Master

    Reference Design

    I2C Bus Master

    Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device
    I2C Bus Master
  • I2C Master - WISHBONE Compatible

    Reference Design

    I2C Master - WISHBONE Compatible

    Based on the OpenCores I2C master core, this Reference Design provides a bridge between the I2C and WISHBONE bus
    I2C Master - WISHBONE Compatible
  • Color Space Converter (CSC)

    IP Core

    Color Space Converter (CSC)

    Free IP core - supports color space conversion and related CODEC functions from 8-16 bits wide, precision up to 18 bits. RGB YCbCr CMYK and more.
    Color Space Converter (CSC)
  • Helion IONOS Image Signal Processing IP Portfolio

    IP Core

    Helion IONOS Image Signal Processing IP Portfolio

    Comprehensive, high-quality, highly-configurable ISP solution from Helion Vision, from basic to advanced High Dynamic Range Imaging (HDRI) color pipelines.
    Helion IONOS Image Signal Processing IP Portfolio
  • FFT Compiler

    IP Core

    FFT Compiler

    Can be configured to perform forward FFT, inverse FFT (IFFT) or port selectable forward/inverse FFT. High-performance streaming and low-resource burst modes.
    FFT Compiler
  • FIR Filter Generator

    IP Core

    FIR Filter Generator

    Highly configurable, multi-channel FIR filter. Supports up to 256 channels each with 2048 taps. Input and coefficient widths from 4 to 32 bits.
    FIR Filter Generator
  • LatticeMico32 Open, Free 32-Bit Soft Processor

    IP Core

    LatticeMico32 Open, Free 32-Bit Soft Processor

    A 32-bit Harvard, RISC architecture soft microprocessor, available for free with an open IP core license. Many compatible modules and IP are available.
    LatticeMico32 Open, Free 32-Bit Soft Processor
  • CORDIC

    IP Core

    CORDIC

    A simple and efficient algorithm to calculate hyperbolic and trigonometric functions and convert polar co-ordinates to cartesian and vice versa
    CORDIC
  • Scatter-Gather DMA Controller

    IP Core

    Scatter-Gather DMA Controller

    Implements a configurable, multi-channel, WISHBONE-compliant DMA controller with scatter-gather capability
    Scatter-Gather DMA Controller
  • Video Frame Buffer

    IP Core

    Video Frame Buffer

    Highly-configurable solution buffers video data in external memory, supports image sizes up to 4K x 4K with YCbCr 4:2:2, 4:4:4 and RGB video formats
    Video Frame Buffer
  • HWD-XP2-USB by JK Hardware Design

    Board

    HWD-XP2-USB by JK Hardware Design

    General purpose evaluation and development platform for LatticeXP2
    HWD-XP2-USB by JK Hardware Design
  • Simple Sigma-Delta ADC

    Reference Design

    Simple Sigma-Delta ADC

    Implements an Analog-to-Digital (ADC) using on-FPGA differntial LVDS inputs (or inexpensive analog comparitor). Save cost by eliminating external ADC devices.
    Simple Sigma-Delta ADC
  • UART - WISHBONE Compatible

    Reference Design

    UART - WISHBONE Compatible

    UART (Universal Asynchronous Receiver/Transmitter) provides both Rx and Tx between the WISHBONE system bus and an RS232 serial communication channel.
    UART - WISHBONE Compatible
  • Universal Asynchronous Receiver/Transmitter

    Reference Design

    Universal Asynchronous Receiver/Transmitter

    Fully configurable UART functionally compatible with the NS16450 UART
    Universal Asynchronous Receiver/Transmitter
  • Gamma Corrector

    IP Core

    Gamma Corrector

    A highly-parameterizable, multi-color plane gamma correction system. It can support almost any custom gamma correction requirement
    Gamma Corrector
  • SDR SDRAM Controller - Advanced

    Reference Design

    SDR SDRAM Controller - Advanced

    Provides a simple generic system interface to the bus master, reducing the user's effort to deal with the SDRAM command interface.
    SDR SDRAM Controller - Advanced
  • 2D Scaler

    IP Core

    2D Scaler

    Highly-configurable design to convert input video frames of one size to output video frames of a different size
    2D Scaler
  • BSCAN - Multiple Port Linker (BSCAN2)

    Reference Design

    BSCAN - Multiple Port Linker (BSCAN2)

    Implements an IEEE 1149.1 compliant Boundary Scan port on an FPGA. Multiple scan ports are linked together feeing into the IEEE 1149.1 port.
    BSCAN - Multiple Port Linker (BSCAN2)
  • I2C Bus Controller for Serial EEPROMs

    Reference Design

    I2C Bus Controller for Serial EEPROMs

    Provides an interface between standard microprocessors and I2C Serial EEPROM devices
    I2C Bus Controller for Serial EEPROMs
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