Coordinate Rotational Digital Computer (CORDIC) IP Core

Uses Full Precision Arithmetic Internally While Supporting Variable Output Precision

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The Lattice CORDIC IP is configurable and several functions can be implemented in the IP core: Rotation, Translation, Sin and Cos, Arctan. Two architecture configurations are available for the arithmetic unit: Parallel, with single cycle data throughput, and Word-serial, with multiple cycles throughput. The input data, output data widths and iterative number are configurable over a wide range. The IP core uses full internal precision while allowing variable output precision with several choices for rounding.

Latest Resource Utilization details are available in the IP Core User Guide.

Features

  • Functions supported:
    • Vector rotation (polar to rectangular)
    • Vector translation (rectangular to polar)
    • Sin and cos
    • Arctan
  • Input data widths from 8 to 32 bits
  • Optional amplitude compensation scaling module to compensate for CORDIC algorithm’s output amplitude scale factor
  • Selectable rounding : Truncation, Rounding Up, Rounding away from zero, Convergent Rounding
  • Parallel architectural configuration for high throughput

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Block Diagram

CORDIC IP Core Block DiagramExpand Image

Resource Utilization

Avant Family
LAV-AT-500E-1LFG1156I
Configuration Clk Fmax (MHz)* Registers LUTs DSP
Default 201.45 1165 1710 0
Mode: Translation,
Others = Default		 201.45 1153 1458 0
Mode: Sin/Cos,
Others = Default		 201.45 1003 1446 0
Mode: Arctan,
Others = Default		 201.45 1080 1414 0
Compensation: DSP-based,
Rounding Method: Convergent,
Synchronous Reset: true,
Clock Enable: true,
Others = Default		 201.45 1610 3099 8

*Note: Fmax is generated when the FPGA design only contains CORDIC IP Core, and the target frequency is 200MHz. These values may be reduced when user logic is added to the FPGA design.

Nexus Family
LIFCL-40-9BG400I
Configuration Clk Fmax (MHz)* Registers LUTs DSP
Default 200 1157 1334 0
Mode: Translation,
Others = Default		 200 1145 1320 0
Mode: Sin/Cos,
Others = Default		 200 1003 1146 0
Architecture= Word-Serial,
Others = Default		 200 302 585 0
Compensation: DSP-based,
Others = Default		 200 1242 1311 8

Note: Fmax is generated when the FPGA design only contains CORDIC IP Core, and the target frequency is 100 MHz. These values may be reduced when user logic is added to the FPGA design

LFD2NX-40-9BG256I
Configuration Clk Fmax (MHz)* Registers LUTs DSP
Default 200 1157 1334 0
Mode: Translation,
Others = Default		 200 1145 1320 0
Mode: Sin/Cos,
Others = Default		 200 1003 1146 0
Mode: Arctan,
Others = Default		 200 302 585 0
"Compensation: DSP-based,
Rounding Method: Convergent,
Synchronous Reset: true,
Clock Enable: true,
Others = Default		 200 1242 1311 8

Note: Fmax is generated when the FPGA design only contains CORDIC IP Core, and the target frequency is 100 MHz. These values may be reduced when user logic is added to the FPGA design

LFMXO5-25-9BBG400I
Configuration Clk Fmax (MHz)* Registers LUTs DSP
Default 200 1157 1334 0
Mode: Translation,
Others = Default		 200 1145 1320 0
Mode: Sin/Cos,
Others = Default		 200 1003 1146 0
Mode: Arctan,
Others = Default		 200 1072 1276 0
"Compensation: DSP-based,
Rounding Method: Convergent,
Synchronous Reset: true,
Clock Enable: true,
Others = Default		 197 1437 2621 8

Note: Fmax is generated when the FPGA design only contains CORDIC IP Core, and the target frequency is 100MHz. These values may be reduced when user logic is added to the FPGA design.

LFMXO5-25-7BBG400I
Configuration Clk Fmax (MHz)* Registers LUTs DSP
Default 145 1157 1334 0
Mode: Translation,
Others = Default		 156 1145 1320 0
Mode: Sin/Cos,
Others = Default		 153 1003 1146 0
Mode: Arctan,
Others = Default		 158 1072 1276 0
"Compensation: DSP-based,
Rounding Method: Convergent,
Synchronous Reset: true,
Clock Enable: true,
Others = Default		 160.694 1437 2621 8

Note: Fmax is generated when the FPGA design only contains CORDIC IP Core, and the target frequency is 100MHz. These values may be reduced when user logic is added to the FPGA design.

To view the complete Resource Utilization of the CORDIC IP Core, click here to view the datasheet.

Ordering Information

  Part Number
Device Family Multi-site Perpetual Single Seat Annual
Certus-N2 CORDIC-CN2-UT CORDIC-CN2-UX
Avant-G CORDIC-AVG-UT CORDIC-AVG-US
Avant-X CORDIC-AVX-UT CORDIC-AVX-US
Avant-E CORDIC-AVE-UT CORDIC-AVE-US
CrossLink-NX CORDIC-CNX-UT CORDIC-CNX-US
CertusPro-NX CORDIC-CPNX-UT CORDIC-CPNX-US
MachXO5-NX CORDIC-XO5-UT CORDIC-XO5-US
Certus-NX CORDIC-CTNX-UT CORDIC-CTNX-US
ECP5 CORDIC-E5-UT CORDIC-E5-US
LatticeECP3 CORDIC-E3-UT1 CORDIC-E3-US
LatticeECP2 CORDIC-P2-UT1 -
LatticeECP2M CORDIC-PM-UT1 -
LatticeEC/ECP CORDIC-E2-UT1 -
LatticeSC/M CORDIC-SC-UT1 -
LatticeXP2 CORDIC-X2-UT1 -
LatticeXP CORDIC-XM-UT1 -

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

To find out how to purchase the CORDIC IP core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
CORDIC IP User Guide
FPGA-IPUG-02136 1.5 12/20/2024 PDF 768 KB
CORDIC IP Core User Guide
FPGA-IPUG02044 1.4 7/16/2018 PDF 1000.5 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
IPexpress Quick Start Guide
8/5/2010 PDF 304.8 KB

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