Coordinate Rotational Digital Computer (CORDIC) IP Core

Uses Full Precision Arithmetic Internally While Supporting Variable Output Precision

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CORDIC（座標回転デジタルコンピュータ）は双曲線関数や三角関数を計算し、極座標をデカルト座標に変換したり、その逆を行うシンプルで効率的なアルゴリズムです。加算、減算、ビットシフト、テーブルルックアップなどの単純な算術演算を必要とする反復法です。これにより、より複雑なタスクの使用向けに、デバイス内で可能な乗算器の制限がなくなります。

ラティスのCORDIC IPは構成可能で、いくつかの機能をIPコアに実装できます：回転、変換、サイン/コサイン、逆正接関数など。2つのアーキテクチャ構成は演算装置で利用可能です：シングルサイクルデータスループットを備えた並列、複数サイクルスループットを備えたワードシリアルなど。入出力データ幅、および反復数は広範囲にわたって設定可能です。IPコアは完全な内部精度を使用しながら、四捨五入のためのいくつかの選択をもつ可変出力精度を可能にします。

機能

  • 対応機能：
    • ベクトル回転（極座標から直交座標）
    • ベクトル並進（直交座標から極座標）
    • サイン/コサイン
    • 逆正接関数
  • 8~32ビットの入力データ幅
  • 4~32の出力を得るための構成可能な反復数
  • オプションのプレ回転モジュール
  • CORDICアルゴリズムの出力振幅スケールファクタを補正するためのオプションの振幅補正スケーリングモジュール
  • 選択可能な四捨五入アルゴリズム：切捨、切上、小数点以下切り下げ、最も近い偶数の整数への丸め
  • スループット最適化のための選択可能な並列アーキテクチャ構成
  • 面積最適化のための選択可能なワードシリアルアーキテクチャ構成
  • 符号付き2の補数データ
  • オプションのクロックイネーブル（ce）および同期リセット（sr）制御信号
  • 全精度の内部演算

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Block Diagram

CORDIC IP Core Block DiagramExpand Image

Resource Utilization

Avant Family
LAV-AT-500E-1LFG1156I
Configuration Clk Fmax (MHz)* Registers LUTs DSP
Default 201.45 1165 1710 0
Mode: Translation,
Others = Default		 201.45 1153 1458 0
Mode: Sin/Cos,
Others = Default		 201.45 1003 1446 0
Mode: Arctan,
Others = Default		 201.45 1080 1414 0
Compensation: DSP-based,
Rounding Method: Convergent,
Synchronous Reset: true,
Clock Enable: true,
Others = Default		 201.45 1610 3099 8

*Note: Fmax is generated when the FPGA design only contains CORDIC IP Core, and the target frequency is 200MHz. These values may be reduced when user logic is added to the FPGA design.

Nexus Family
LIFCL-40-9BG400I
Configuration Clk Fmax (MHz)* Registers LUTs DSP
Default 200 1157 1334 0
Mode: Translation,
Others = Default		 200 1145 1320 0
Mode: Sin/Cos,
Others = Default		 200 1003 1146 0
Architecture= Word-Serial,
Others = Default		 200 302 585 0
Compensation: DSP-based,
Others = Default		 200 1242 1311 8

Note: Fmax is generated when the FPGA design only contains CORDIC IP Core, and the target frequency is 100 MHz. These values may be reduced when user logic is added to the FPGA design

LFD2NX-40-9BG256I
Configuration Clk Fmax (MHz)* Registers LUTs DSP
Default 200 1157 1334 0
Mode: Translation,
Others = Default		 200 1145 1320 0
Mode: Sin/Cos,
Others = Default		 200 1003 1146 0
Mode: Arctan,
Others = Default		 200 302 585 0
"Compensation: DSP-based,
Rounding Method: Convergent,
Synchronous Reset: true,
Clock Enable: true,
Others = Default		 200 1242 1311 8

Note: Fmax is generated when the FPGA design only contains CORDIC IP Core, and the target frequency is 100 MHz. These values may be reduced when user logic is added to the FPGA design

LFMXO5-25-9BBG400I
Configuration Clk Fmax (MHz)* Registers LUTs DSP
Default 200 1157 1334 0
Mode: Translation,
Others = Default		 200 1145 1320 0
Mode: Sin/Cos,
Others = Default		 200 1003 1146 0
Mode: Arctan,
Others = Default		 200 1072 1276 0
"Compensation: DSP-based,
Rounding Method: Convergent,
Synchronous Reset: true,
Clock Enable: true,
Others = Default		 197 1437 2621 8

Note: Fmax is generated when the FPGA design only contains CORDIC IP Core, and the target frequency is 100MHz. These values may be reduced when user logic is added to the FPGA design.

LFMXO5-25-7BBG400I
Configuration Clk Fmax (MHz)* Registers LUTs DSP
Default 145 1157 1334 0
Mode: Translation,
Others = Default		 156 1145 1320 0
Mode: Sin/Cos,
Others = Default		 153 1003 1146 0
Mode: Arctan,
Others = Default		 158 1072 1276 0
"Compensation: DSP-based,
Rounding Method: Convergent,
Synchronous Reset: true,
Clock Enable: true,
Others = Default		 160.694 1437 2621 8

Note: Fmax is generated when the FPGA design only contains CORDIC IP Core, and the target frequency is 100MHz. These values may be reduced when user logic is added to the FPGA design.

To view the complete Resource Utilization of the CORDIC IP Core, click here to view the datasheet.

Ordering Information

  Part Number
Device Family Multi-site Perpetual Single Seat Annual
Avant-G CORDIC-AVG-UT CORDIC-AVG-US
Avant-X CORDIC-AVX-UT CORDIC-AVX-US
Avant-E CORDIC-AVE-UT CORDIC-AVE-US
CrossLink-NX CORDIC-CNX-UT CORDIC-CNX-US
CertusPro-NX CORDIC-CPNX-UT CORDIC-CPNX-US
MachXO5-NX CORDIC-XO5-UT CORDIC-XO5-US
Certus-NX CORDIC-CTNX-UT CORDIC-CTNX-US
ECP5 CORDIC-E5-UT CORDIC-E5-US
LatticeECP3 CORDIC-E3-UT1 CORDIC-E3-US
LatticeECP2 CORDIC-P2-UT1 -
LatticeECP2M CORDIC-PM-UT1 -
LatticeEC/ECP CORDIC-E2-UT1 -
LatticeSC/M CORDIC-SC-UT1 -
LatticeXP2 CORDIC-X2-UT1 -
LatticeXP CORDIC-XM-UT1 -

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

To find out how to purchase the CORDIC IP core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
CORDIC IP Core - User Guide
FPGA-IPUG-02136 1.4 12/5/2023 PDF 730.4 KB
CORDIC IP Core User Guide
FPGA-IPUG02044 1.4 7/16/2018 PDF 1000.5 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
IPexpress Quick Start Guide
8/5/2010 PDF 304.8 KB

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