The Universal Asynchronous Receiver Transmitter (UART) is a popular and widely used device for data communication in the field of telecommunication. There are different versions of UARTs in the industry. Some of them contain FIFOs for the receiver/transmitter data buffering and some of them have the 9 data bits mode (start bit + 9 data bits + parity + stop bits).
This reference design describes a fully configurable UART optimized for and implemented in a variety of Lattice devices, which offer superior performance and architecture compared to existing semiconductor ASSPs (application-specific standard products).
Transmitter - Transmitter enabled by new data write to transmit holding register. This serial data frame (start bit + data bits + parity bit + stop bit) will be transmitted at the rate of 1/16 of Clk16X frequency.
Receiver - Receiver synchronizes off the start bit and samples all incoming bits at the center of each bit. The internal clock Clk16X is 16 times the receiving/transmitting baud rate clock frequency, the start bit needs to be low at least eight Clk16X clocks to be considered as a valid start bit.
Interrupt - The UART prioritizes interrupts into four levels to minimize external software interaction, and records these in the Interrupt Identification Register (IIR). The four levels of interrupt conditions in order of priority are Receiver Line Status; Received Data Ready; Transmitter Holding Register Empty and MODEM Status. Separate interrupt lines for data received (RxRdyn) and data transmitted (TxRdyn).