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  • Certus-N2评估板

    Board

    Certus-N2评估板

    Certus-N2评估板专为Certus-N2的评估和开发而设计,支持16G Serdes、LPDDR4和PCI-Gen4。
    Certus-N2评估板
  • ​​M-PESTI Initiator IP核

    IP Core

    ​​M-PESTI Initiator IP核

    莱迪思M-PESTI IP核可在系统启动前检测外设存在和属性采集。
    ​​M-PESTI Initiator IP核
  • Human to Machine Interfacing Demonstration

    演示

    Human to Machine Interfacing Demonstration

    Human-to-machine interface demo uses FPGA-accelerated NN models for detecting, positioning, and identifying persons.
    Human to Machine Interfacing Demonstration
  • MPESTI Initiator Reference Design

    Reference Design

    MPESTI Initiator Reference Design

    MPESTI Initiator Reference Design provides the solution template which is compliant with the MPESTI Base Specification.
    MPESTI Initiator Reference Design
  • LVDS Tunneling Protocol and Interface Reference Design

    Reference Design

    LVDS Tunneling Protocol and Interface Reference Design

    The DC-SCM 2.0 LTPI Reference Design provides multiple solution compliant with DC-SCM 2.0 with a standardized DC-SCI and aggregating multiple data channels.
    LVDS Tunneling Protocol and Interface Reference Design
  • Single Wire Signal Aggregation Demonstration

    演示

    Single Wire Signal Aggregation Demonstration

    Single Wire Signal Aggregation Demonstration contains two boards to demonstrate the complete working design in a stand-alone configuration.
    Single Wire Signal Aggregation Demonstration
  • Joint Test Action Group (JTAG) Bridge IP Core

    IP Core

    Joint Test Action Group (JTAG) Bridge IP Core

    The Lattice Semiconductor JTAG Bridge IP provides an efficient solution for debugging on-board issues by allowing you to access memory and peripheral registers directly using this IP, without involving the processor.
  • 莱迪思Mach-NX Sentry可信根参考设计

    Reference Design

    莱迪思Mach-NX Sentry可信根参考设计

    该设计利用平台固件保护恢复可信根来帮助开发和测试一个完整的符合NIST 800-193标准的安全系统,该系统具有保护、检测和恢复功能。
    莱迪思Mach-NX Sentry可信根参考设计
  • RISC-V Single Core Linux (SCL) Processor

    IP Core

    RISC-V Single Core Linux (SCL) Processor

    RISC-V Single Core Linux processor includes everything required for running Linux on Lattice FPGAs and supports the RV32IMAC and RV32GC architecture.
    RISC-V Single Core Linux (SCL) Processor
  • iCEstick评估套件

    Board

    iCEstick评估套件

    一款低成本、使用USB接口,带有一片iCE40HX-1k的iCE40评估板
    iCEstick评估套件
  • 8N1 UART Transceiver Reference Design

    Reference Design

    8N1 UART Transceiver Reference Design

    8-bit data, no parity, and 1 stop bit Universal Asynchronous Receiver/Transmitter (UART) performs serial-to-parallel and parallel to serial conversions on data characters received from a peripheral device or CPU
    8N1 UART Transceiver Reference Design
  • CrossLink-NX PCIe桥接板

    Board

    CrossLink-NX PCIe桥接板

    将多种标准IO桥接至PCIe的互连开发平台
    CrossLink-NX PCIe桥接板
  • MAS LIFCL Evaluation Board

    Board

    MAS LIFCL Evaluation Board

    This modular, flexible and easy-to-use CrossLink-NX 17 board is designed for video applications, including CSI2 MIPI, LVDS HDMI (through PMOD).
    MAS LIFCL Evaluation Board
  • UART IP核

    IP Core

    UART IP核

    Propel IP模块:类似于NS16450 UART的串行通信,支持RS-232。
    UART IP核
  • LXO2000

    Board

    LXO2000

    The TEL0001 "LXO2000" is a low cost FPGA module integrating a Lattice XO2-4000 and on-board USB/JTAG. It's compatible to the Arduino MKR standard.
    LXO2000
  • UART 16550 IP核

    IP Core

    UART 16550 IP核

    可配置的UART端口。与PC16550D兼容。7或8位数据宽度,Tx有1、1.5、2个停止位。多个奇偶校验和波特率选项。
    UART 16550 IP核
  • DCP1000 - Data Capture and Playback Module

    Board

    DCP1000 - Data Capture and Playback Module

    DCP1000 is a compact, user-friendly Data Capture & Playback Card for mmWave radars, built on Lattice Nexus, featuring CertusPro-NX with 100K logic cells & DDR4.
    DCP1000 - Data Capture and Playback Module
  • DCA1000 Evaluation Module

    Board

    DCA1000 Evaluation Module

    The DCA1000EVM receives LVDS-format radar-sensing data and can stream over Ethernet in real-time. The board also connects to TI’s 77GHz xWR1xxx EVM.
    DCA1000 Evaluation Module
  • LatticeMico32开放、免费的32位软处理器

    IP Core

    LatticeMico32开放、免费的32位软处理器

    A 32-bit Harvard, RISC architecture soft microprocessor, available for free with an open IP core license. Many compatible modules and IP are available.
    LatticeMico32开放、免费的32位软处理器
  • 传感器数据缓存

    Reference Design

    传感器数据缓存

    iCE40 UltraPlus™器件可用于实现低成本、低功耗、小尺寸的传感器中心,支持聚合来自多种数字传感器的数据。
    传感器数据缓存
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