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  • Modular Peripheral Sideband Tunneling Interface (M-PESTI) IP core

    IP Core

    Modular Peripheral Sideband Tunneling Interface (M-PESTI) IP core

    ​​The Lattice M-PESTI IP core provides early peripheral presence detection and attribute collection before system boot up.​
    Certus-N2, Avant-G, Avant-X, Avant-E, MachXO5-NX, MachXO3D, MachXO3, Mach-NX 
    MPESTI, UART, APB, Lattice Sentry, OCP 
    Modular Peripheral Sideband Tunneling Interface (M-PESTI) IP core
  • FOC Motor Control Reference Design

    Reference Design

    FOC Motor Control Reference Design

    The Field-Oriented Control (FOC) Motor Control reference design comprises a complete RISC-V embedded system integrated with the FOC Motor Control IP.
    Certus-NX 
    FOC, RISC-V, MATLAB, UART 
  • Human to Machine Interfacing Demonstration

    Demo

    Human to Machine Interfacing Demonstration

    Human-to-machine interface demo uses FPGA-accelerated NN models for detecting, positioning, and identifying persons.
    CrossLink-NX 
    NN Models, Person Detection, UART, Lattice sensAI, sensAIEdgeVisionSDK 
    Human to Machine Interfacing Demonstration
  • MPESTI Initiator Reference Design

    Reference Design

    MPESTI Initiator Reference Design

    The design specifically targets MIPI CSI-2 camera sensors and offers a flexible architecture capable of integrating multiple camera inputs based on system requirements.
    Avant-E, MachXO5-NX, MachXO3, MachXO3D 
    MPESTI, UART, APB, AHB, RISC-V, OCP 
    MPESTI Initiator Reference Design
  • LVDS Tunneling Protocol and Interface Reference Design

    Reference Design

    LVDS Tunneling Protocol and Interface Reference Design

    The DC-SCM 2.0 LTPI Reference Design provides multiple solution compliant with DC-SCM 2.0 with a standardized DC-SCI and aggregating multiple data channels.
    MachXO5-NX, MachXO3D, MachXO3, Mach-NX 
    CRC, LVDS, I2C, GPIO, UART, LTPI, AMBA, APB, Lattice Diamond, Lattice Propel, OCP 
    LVDS Tunneling Protocol and Interface Reference Design
  • Single Wire Signal Aggregation Demonstration

    Demo

    Single Wire Signal Aggregation Demonstration

    Single Wire Signal Aggregation Demonstration contains two boards to demonstrate the complete working design in a stand-alone configuration.
    iCE40 UltraPlus 
    Single Wire, Signal Aggregation, Bus Controllers, GPIO, I2C, I2S, UART, Defense 
    Single Wire Signal Aggregation Demonstration
  • Joint Test Action Group (JTAG) Bridge IP Core

    IP Core

    Joint Test Action Group (JTAG) Bridge IP Core

    The Lattice Semiconductor JTAG Bridge IP provides an efficient solution for debugging on-board issues by allowing you to access memory and peripheral registers directly using this IP, without involving the processor.
    Certus-N2, Avant-E, Avant-G, Avant-X, MachXO5-NX, CertusPro-NX, Certus-NX, CrossLink-NX 
    JTAG, AXI4, UART, Lattice Propel 
  • RISC-V Single Core Linux (SCL) Processor

    IP Core

    RISC-V Single Core Linux (SCL) Processor

    RISC-V Single Core Linux processor includes everything required for running Linux on Lattice FPGAs and supports the RV32IMAC and RV32GC architecture.
    CertusPro-NX 
    RISC-V, Soft Processor, DDR Memories, AHB, AHB-Lite, AMBA, AXI, GPIO Control, UART 
    RISC-V Single Core Linux (SCL) Processor
  • Single Wire Signal Aggregation Development Board

    Board

    Single Wire Signal Aggregation Development Board

    Single Wire Signal Aggregation Dev Board uses the smallest form factor FPGAs to perform as a Single-Wire aggregator for I2C, I2S, UART, & GPIO signaling.
    iCE40 UltraPlus 
    Single Wire, Signal Aggregation, Bus Controllers, GPIO, I2C, I2S, UART, Defense, Avionics 
  • iCEstick Evaluation Kit

    Board

    iCEstick Evaluation Kit

    A low-cost platform for evaluation and development with the iCE40 FPGA. Plus directly into a USB port for power and data communication.
    iCE40 LP/HX 
    Breakout, IrDA, PMOD, UART 
    iCEstick Evaluation Kit
  • 8N1 UART Transceiver Reference Design

    Reference Design

    8N1 UART Transceiver Reference Design

    8-bit data, no parity, and 1 stop bit Universal Asynchronous Receiver/Transmitter (UART) performs serial-to-parallel and parallel to serial conversions on data characters received from a peripheral device or CPU
    iCE40 UltraPlus, MachXO2 
    UART, Bus Controllers, TOR Switch 
    8N1 UART Transceiver Reference Design
  • MAS LIFCL Evaluation Board

    Board

    MAS LIFCL Evaluation Board

    This modular, flexible and easy-to-use CrossLink-NX 17 board is designed for video applications, including CSI2 MIPI, LVDS HDMI (through PMOD).
    CrossLink-NX 
    PMOD, LED Control, SPI Flash, I2C, SPI, UART, CSI-2, DisplayPort, DSI, HDMI, Image Processing, LVDS Video, MIPI, Video Bridge, Video Tx/Rx 
    MAS LIFCL Evaluation Board
  • UART IP Core

    IP Core

    UART IP Core

    Propel IP Module: Similar to NS16450 UART for serial communication supporting RS-232.
    MachXO3D, Certus-NX, CrossLink-NX, Mach-NX, MachXO2, MachXO3, Certus-N2, MachXO4 
    APB, RS-232, AMBA, Lattice Propel, UART, TOR Switch, Defense, Automotive 
    UART IP Core
  • LXO2000

    Board

    LXO2000

    The TEL0001 "LXO2000" is a low cost FPGA module integrating a Lattice XO2-4000 and on-board USB/JTAG. It's compatible to the Arduino MKR standard.
    MachXO2 
    UART, SPI, LED Control, Arduino, PMOD, Breakout 
    LXO2000
  • UART 16550 IP Core

    IP Core

    UART 16550 IP Core

    ​​Lattice UART16550 IP Core is designed for use in serial communication, supporting the RS-232, RS-422, RS-485, and Electronic Industries Association (EIA) standards, among others.​
    iCE40 UltraPlus, CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX 
    Bus Controllers, UART, TOR Switch, Guidance Systems, Automotive, Space, Satellite Communications, Launchers, Smart munitions 
    UART 16550 IP Core
  • DCA1000 Evaluation Module

    Board

    DCA1000 Evaluation Module

    The DCA1000EVM receives LVDS-format radar-sensing data and can stream over Ethernet in real-time. The board also connects to TI’s 77GHz xWR1xxx EVM.
    ECP5 / ECP5-5G 
    Object Counting, Object Detection, Object Identification, Object Tracking, Machine Vision, ADAS, FPGA, RJ-45, Ethernet, DDR SDRAM, Embedded FPGA Flash, SD Memory, SPI Flash, SPI, UART, LVDS Video, Radar 
    DCA1000 Evaluation Module
  • LatticeMico32 Open, Free 32-Bit Soft Processor

    IP Core

    LatticeMico32 Open, Free 32-Bit Soft Processor

    A 32-bit Harvard, RISC architecture soft microprocessor, available for free with an open IP core license. Many compatible modules and IP are available.
    LatticeECP3, LatticeXP2, LatticeECP2/M 
    GPIO Control, Mico, Soft Processor, UART, Wishbone, TOR Switch, Defense 
    LatticeMico32 Open, Free 32-Bit Soft Processor
  • ProFRAME CamAD3 Camera Adapters

    Board

    ProFRAME CamAD3 Camera Adapters

    ProFRAME camera adapters are mounted on the base board of the proFRAME video grabber and playback system. Supports GMSL 1/2/3 and FPD-Link III/IV interfaces.
    MachXO3 
    Infrared LED, LED Control, GPIO Control, I2C, SPI, UART, Wishbone, CSI-2, Image Processing, MIPI, Video Bridge 
    ProFRAME CamAD3 Camera Adapters
  • UART Reference Design

    Reference Design

    UART Reference Design

    The UART reference design describes a fully configurable UART optimized for and implemented in a variety of Lattice devices.
    ispMACH 4000ZE, MachXO, LatticeXP2, Platform Manager, MachXO5-NX, MachXO2 
    Bus Controllers, UART 
    UART Reference Design
  • STEP-MXO2 Development Board

    Board

    STEP-MXO2 Development Board

    A small, breadboard friendly 40-pin DIP form factor board build around Lattice MachXO2. Available in China only.
    MachXO2 
    UART 
    STEP-MXO2 Development Board
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