RISC-V Single Core Linux (SCL) Processor

Bluespec’s RISC-V Single Core Linux processor includes everything required for running Linux on Lattice FPGAs

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RISC-V Single Core Linux (SCL) CPU - Soft processor which supports the RV32I (Integer) instruction set with M (Multiply), A (Atomic), C (Compressed), and optional F (Floating Point – Single Precision) and D (Floating point – double precision) instructions. The RISC-V SCL processor also includes timers (CLINT) and a Programmable Interrupt Controller (PLIC) and an optional Debug Unit.

Standard interfaces - The SCL is has multiple configurable bus interfaces, including AXI, AHB, and APB and utilizes Lattice DDR controllers to interface with external memory for program and data store. L1 and L2 caches are supported and configurable based on application requirements.

Lattice Tool Integration - The design is implemented in Verilog HDL. It can be targeted to the CrossLink-NX family and future generation Lattice FPGAs and implemented using the Lattice Radiant Place and Route tool integrated with the Synplify Pro synthesis tool.


  • RISC-V with 5-Stage Instruction Pipeline
  • RV32IMAC and RV32GC
  • Supports User, Supervisor, and Machine Modes
  • Only soft processor that can run Linux on Lattice FPGAs
  • 2.4 CoreMark/MHz
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