Serial Communications Receiver and Transmitter IP

The Lattice Semiconductor UART (Universal Asynchronous Receiver/Transmitter) IP Core is designed for use in serial communication, supporting the RS-232. The UART IP Core has many characteristics similar to those of the NS16450 UART.

To preserve FPGA resources, the UART IP Core is not identical to the NS16450 UART. As such, it is not source code compatible. This means the existing driver code for the NS16450 UART does not work on the Lattice UART IP Core.

The design is implemented in Verilog HDL. The IP can be configured and generated using Lattice Propel Builder. It can be targeted to MachXO3D FPGA devices and implemented using the Lattice Diamond® software Place and Route tool integrated with the Synplify Pro synthesis tool.


  • APB 1.0 interface
  • Similarity with the National Semiconductor NS16450 UART
  • Insertion or extraction of standard asynchronous communication bits (start, stop, and parity) to or from the serial data
  • Fully prioritized interrupt system control
  • Fully programmable serial interface characteristics
  • Configurable Baud Rate support for Standard and Custom modes
Lattice Propel

Block Diagram

UART IP Core Block Diagram


Quick Reference
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UART IP Core - Lattice Propel Builder
FPGA-IPUG-02105 1.2 5/11/2021 PDF 915.1 KB

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