UART IP Core

Serial Communications Receiver and Transmitter IP

Related Products

The Lattice Semiconductor UART (Universal Asynchronous Receiver/Transmitter) IP Core is designed for use in serial communication, supporting the RS-232. The UART IP Core has many characteristics similar to those of the NS16450 UART. To preserve FPGA resources, the UART IP Core is not identical to the NS16450 UART.

Resource Utilization details are available in the IP Core User Guide.

Features

  • APB 1.0 interface
  • Similarity with the National Semiconductor NS16450 UART with different register addresses
  • Optional 16-word-deep FIFO implemented in the UART transmit/receive path when FIFO mode is selected
  • Insertion or extraction of standard asynchronous communication bits (start, stop, and parity) to or from the serial data
  • Holding and shifting registers, which eliminate the need for precise synchronization between the host (APB interface) and serial data

Block Diagram

UART IP Core Block Diagram

Ordering Information

The UART IP is provided at no additional cost with the Lattice Radiant software.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
UART IP Core - User Guide
FPGA-IPUG-02105 1.3 7/7/2024 PDF 471.5 KB

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