UART IP Core

Serial Communications Receiver and Transmitter IP

Related Products

The Lattice Semiconductor UART IP core is designed for use in serial communication and supports the RS-232 protocol. The IP shares many characteristics with the NS16450 UART; however, to conserve FPGA resources, the IP is not identical to the NS16450 UART. As a result, it is not source-code compatible, meaning existing driver code for the NS16450 UART does not work on the Lattice UART IP core.

Features

  • APB 1.0 interface
  • Similarity with the National Semiconductor NS16450 UART with different register addresses
  • Optional 16-word-deep FIFO implemented in the UART transmit/receive path when FIFO mode is selected
  • Insertion or extraction of standard asynchronous communication bits (start, stop, and parity) to or from the serial data
  • Holding and shifting registers, which eliminate the need for precise synchronization between the host (APB interface) and serial data

Block Diagram

UART IP Core Block Diagram

Ordering Information

The UART IP is provided at no additional cost with the Lattice Radiant software.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
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UART IP Core - User Guide
FPGA-IPUG-02105 1.6 12/11/2025 PDF 1.4 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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UART IP Core - Release Notes
FPGA-RN-02023 1.1 12/11/2025 PDF 246.4 KB

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