The Lattice Semiconductor UART (Universal Asynchronous Receiver/Transmitter) IP Core is designed for use in serial communication, supporting the RS-232. The UART IP Core has many characteristics similar to those of the NS16450 UART.
To preserve FPGA resources, the UART IP Core is not identical to the NS16450 UART. As such, it is not source code compatible. This means the existing driver code for the NS16450 UART does not work on the Lattice UART IP Core.
The design is implemented in Verilog HDL. The IP can be configured and generated using Lattice Propel Builder. It can be targeted to MachXO3D FPGA devices and implemented using the Lattice Diamond® software Place and Route tool integrated with the Synplify Pro synthesis tool.