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  • CSI-2/DSI D-PHY Receiver

    IP Core

  • SubLVDS Image Sensor Receiver

    IP Core

    SubLVDS Image Sensor Receiver

    Modular MIPI/D-PHY IP - Converts SubLVDS Image Sensor Video Stream to Pixel Clock Domain
    SubLVDS Image Sensor Receiver
  • I3C Master IP Core

    IP Core

    I3C Master IP Core

    Bus controller following the MIPI I3C specification. Up to 12.5 MHz Push-Pull, legacy I2C support, Multi-master capability, In-Band Interrupt, Hot-join and more
    I3C Master IP Core
  • I3C Slave IP Core

    IP Core

    I3C Slave IP Core

    Interfaces to the MIPI I3C specification. Up to 12.5 MHz Push-Pull, legacy I2C support, Multi-master capability, In-Band Interrupt, Hot-join and more
    I3C Slave IP Core
  • 10Gb Ethernet PCS IP Core

    IP Core

    10Gb Ethernet PCS IP Core

    The 10Gb Ethernet PCS IP Core provides XGMII interface to MAC and follows IEEE802.3 10G Base-R standard.
    10Gb Ethernet PCS IP Core
  • Memory Controller IP Core

    IP Core

    Memory Controller IP Core

    The Lattice Semiconductor Memory Controller Interface module provides a solution to interface to DDR3 or LPDDR4 DDR memory standards.
    Memory Controller IP Core
  • Multi-Port Arbiter for DDR3 Memory Controller IP Core

    IP Core

    Multi-Port Arbiter for DDR3 Memory Controller IP Core

    The Lattice Semiconductor Memory Controller Interface module provides a solution to interface to DDR3 or LPDDR4 DDR memory standards.
    Multi-Port Arbiter for DDR3 Memory Controller IP Core
  • SLVS-EC Receiver IP Core

    IP Core

    SLVS-EC Receiver IP Core

    The SLVS-EC RX IP provides the FPGA an interface to receive serial data from CMOS Image Sensors and offers a solution to convert the incoming serial data to a parallel pixel data format.
    SLVS-EC Receiver IP Core
  • SPI Flash Memory Controller IP Core

    IP Core

    SPI Flash Memory Controller IP Core

    The Serial Peripheral Interface (SPI) flash memory controller provides an industry-standard interface between a central processing unit (CPU) and an off-chip SPI flash memory device.
    SPI Flash Memory Controller IP Core
  • Watchdog Timer IP Core

    IP Core

    Watchdog Timer IP Core

    Watchdog Timer IP Core is a two-stage timer that will start to count depending on the computer status.
    Watchdog Timer IP Core
  • DisplayPort IP

    IP Core

    DisplayPort IP

    Lattice has partnered with Bitec to bring the DisplayPort 1.4a compliant IP Core (with eDP 1.4 support) to the ECP5 FPGA. Supports resolutions of up to 1080p60
    DisplayPort IP
  • DisplayPort VIP Input Board

    Board

    DisplayPort VIP Input Board

    Expands the Lattice VIP board ecosystem to support DisplayPort 1.4a (DP) video input - up to 4 lanes at 1.62 or 2.7 Gbps.
    DisplayPort VIP Input Board
  • DisplayPort VIP Output Board

    Board

    DisplayPort VIP Output Board

    Expands the Lattice VIP board ecosystem to support DisplayPort 1.4a (DP) video output - up to 4 lanes at 1.62 or 2.7 Gbps.
    DisplayPort VIP Output Board
  • Tri-Speed Ethernet MAC Core IP

    IP Core

    Tri-Speed Ethernet MAC Core IP

    Transmits and receives data between a host processor and an Ethernet network. IEEE 802.3 compliant. Supports 10/100/1000 operation.
    Tri-Speed Ethernet MAC Core IP
  • CertusPro-NX Evaluation Board

    Board

    CertusPro-NX Evaluation Board

    Prototyping Board with Abundant I/O, 10G SERDES, Expansion Headers and 100K Logic Cells
    CertusPro-NX Evaluation Board
  • Lattice mVision CertusPro-NX Video Processing Board

    Board

    Lattice mVision CertusPro-NX Video Processing Board

    A platform that expands support for Lattice based high performance cameras by enabling incorporation of image sensor processing and interfacing with high speed SLVS-EC based sensors, while also enabling incorporation of CoaXPress outputs.
    Lattice mVision CertusPro-NX Video Processing Board
  • GPIO IP Core

    IP Core

    GPIO IP Core

    Detects and controls GPIOs via Lattice Memory Mapped Interface (LMMI) or Advanced Peripheral Bus Interface (APB).
    GPIO IP Core
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