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  • CertusPro-NX Versa Board

    Board

    CertusPro-NX Versa Board

    CertusPro-NX Versa Board supports a wide range industry standards such as MIPI, SFP+, 10 GbE, LPDDR4 and PCIe (Gen3) for rapid prototyping and testing.
    CertusPro-NX Versa Board
  • Object Classification Demonstration

    Demo

    Object Classification Demonstration

    This object classification demo provides a sample application for detecting, classifying, and tracking multiple objects running on CertusPro-NX FPGA.
    Object Classification Demonstration
  • Object Classification Reference Design

    Reference Design

    Object Classification Reference Design

    The Object Classification reference design shows examples on implementing machine-learning based object classification to edge devices applications.
    Object Classification Reference Design
  • PCIe Basic Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe Basic Demo for Lattice Nexus-based FPGAs

    The PCIe Basic Demo allows you to control three 7 segment LEDs and manipulate the onboard memory of the FPGA through the PCIe slot.
    PCIe Basic Demo for Lattice Nexus-based FPGAs
  • PCIe Colorbar Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe Colorbar Demo for Lattice Nexus-based FPGAs

    PCIe Colorbar Demo displays a series of moving colorbars by streaming the image data using DMA transfers from the FPGA to the host system.
    PCIe Colorbar Demo for Lattice Nexus-based FPGAs
  • PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

    Demo

    PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

    The PCI Express DMA Throughput Demo allows to initiate DMA read and write transactions, transferring data from the host to the FPGA and vice versa.
    PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs
  • CertusPro-NX PCIe Bridge Board

    Board

    CertusPro-NX PCIe Bridge Board

    The CertusPro-NX PCIe Bridge Board enables video bridge capabilities to PCIe and embedded vision type applications.
    CertusPro-NX PCIe Bridge Board
  • RISC-V MC CPU IP Core

    IP Core

    RISC-V MC CPU IP Core

    The Lattice RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC).
    RISC-V MC CPU IP Core
  • RISC-V RX CPU IP Core

    IP Core

    RISC-V RX CPU IP Core

    Lattice RISC-V RX IP processes data and instructions while monitoring the external interrupts, using 32-bit RISC-V processor core and several submodules.
    RISC-V RX CPU IP Core
  • RISC-V SM CPU IP Core

    IP Core

    RISC-V SM CPU IP Core

    Lattice RISC-V SM CPU IP core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.
    RISC-V SM CPU IP Core
  • Tightly-Coupled Memory (TCM) IP Core

    IP Core

    Tightly-Coupled Memory (TCM) IP Core

    The Tightly-Coupled Memory IP ensures low-latency automatic selection of the best memory type for user-selected application.
    Tightly-Coupled Memory (TCM) IP Core
  • Advanced CNN Accelerator IP

    IP Core

    Advanced CNN Accelerator IP

    Calculates full layers of Neural Network including convolution layer, pooling layer, batch normalization layer, and fully connected layer.
    Advanced CNN Accelerator IP
  • Barcode Detection Reference Design

    Reference Design

    Barcode Detection Reference Design

    Exhibits the barcode detection using CertusPro-NX Voice & Vision Machine Learning Board & its camera barcode detection potential based on Yolov5 NN models.
    Barcode Detection Reference Design
  • CertusPro-NX Voice and Vision Machine Learning Board

    Board

    CertusPro-NX Voice and Vision Machine Learning Board

    Design AI use cases for the Edge quickly! This board along with the Lattice sensAI solution stack provide the tools for developing vision and audio-based AI applications.
    CertusPro-NX Voice and Vision Machine Learning Board
  • Demo for Lattice ORAN Secure Sync for IEEE 1588 PTP

    Demo

    Demo for Lattice ORAN Secure Sync for IEEE 1588 PTP

    Demo for Lattice ORAN Secure Sync show how Lattice FPGA w/ soft IPs can support tight & secure synchronization using 1588 PTP & ITU profiles for Telecom.
    Demo for Lattice ORAN Secure Sync for IEEE 1588 PTP
  • DisplayPort IP Core

    IP Core

    DisplayPort IP Core

    The Lattice DisplayPort IP Core is designed for transmission and reception of serial-digital video for consumer and professional displays.
    DisplayPort IP Core
  • Image Signal Processing IP Cores Suite

    IP Core

    Image Signal Processing IP Cores Suite

    The Lattice mVision ISP IP Core implements ISP pipelines for image quality enhancements in embedded designs based on Lattice FPGA devices.
    Image Signal Processing IP Cores Suite
  • Lattice ORAN IEEE 1588 PTP Secure Sync Reference Design

    Reference Design

    Lattice ORAN IEEE 1588 PTP Secure Sync Reference Design

    Lattice ORAN 1.1 RD shows how to provide ultra-reliable time synchronization & phase alignment for delivering timing accuracy in 5G ORAN networks.
    Lattice ORAN IEEE 1588 PTP Secure Sync Reference Design
  • Lattice ORAN Timing and Synchronization Kit

    Board

    Lattice ORAN Timing and Synchronization Kit

    ORAN Sync Board has 2x 10GE & 2x 1GE ports, SMA & FMC connectors for testing, demos, development, GNSS & on-board timing sources, ToD, & PPS RJ48 connectors
    Lattice ORAN Timing and Synchronization Kit
  • Lattice ORAN™ Control Demonstration

    Demo

    Lattice ORAN™ Control Demonstration

    Lattice ORAN provides packet authentication, encryption and decryption and support SPDM protocol over MCTP.
    Lattice ORAN™ Control Demonstration
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