QSPI Flash Controller IP Core

Four Times Enhanced Throughput of a Standard SPI

​The Lattice QSPI Flash Controller IP core supports the SPI, DSPI, and QSPI protocols to perform operations on the target flash device. A Quad Serial Peripheral Interface (QSPI) uses four tri-state data lines and is commonly used to program, erase, and read SPI flash memories. QSPI enhances the throughput of a standard SPI by four times since four bits are transferred with every clock cycle.

Resource Utilization details are available in the IP Core User Guide.

Features

  • ​​Different bus interfaces: AMBA 3 AHB-Lite Protocol v1.0, AMBA AXI4-Lite Protocol (for CSR access only), AMBA AXI4 Protocol​
  • ​​Scalable performance: 1X, 2X, 4X I/O widths.​
  • ​​Programmable SPI clock phase and polarity.​
  • ​​Programmable serial clock frequency.​
  • RISC V QSPI code little endian and code execution.

Block Diagram

Resource Utilization

Avant Family
LAV-AT-E70
Interface Registers LUTs EBRs Synthesis Tools
AHB-Lite 1412 2682 0 Synplify Pro 2022.1
AHB-Lite + AXI4-Lite 1542 2741 0 Synplify Pro 2022.1
AXI4 1768 3407 0 Synplify Pro 2022.1
AXI4 + AXI4-Lite 1854 3461 0 Synplify Pro 2022.1
Nexus Family
LFCPNX-100
Interface Registers LUTs EBRs Synthesis Tools
AHB-Lite 1463 2667 0 Synplify Pro 2022.1
AHB-Lite + AXI4-Lite 1544 2721 0 Synplify Pro 2022.1
AXI4 1766 3392 0 Synplify Pro 2022.1
AXI4 + AXI4-Lite 1850 3441 0 Synplify Pro 2022.1

Ordering Information

The QSPI Flash Controller IP Core can be generated and configured in Lattice Propel™ Builder software free of charge.

Documentation

Quick Reference
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QSPI Flash Controller Driver API Reference
FPGA-TN-02339 1.2 8/19/2024 PDF 480.2 KB
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QSPI Flash Controller Driver API Reference
FPGA-TN-02339 1.2 8/19/2024 PDF 480.2 KB
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QSPI Flash Controller IP Core - User Guide
FPGA-IPUG-02248 1.1 8/4/2024 PDF 2.4 MB

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