QSPI Flash Controller IP Core

Four Times Enhanced Throughput of a Standard SPI

​The Lattice QSPI Flash Controller IP core supports the SPI, DSPI, and QSPI protocols to perform operations on the target flash device. A Quad Serial Peripheral Interface (QSPI) uses four tri-state data lines and is commonly used to program, erase, and read SPI flash memories. QSPI enhances the throughput of a standard SPI by four times since four bits are transferred with every clock cycle.

Resource Utilization details are available in the IP Core User Guide.

Features

  • Different bus interfaces:
    • AMBA 3 AHB-Lite Protocol v1.0
    • AMBA AXI4-Lite Protocol (for CSR access only)
    • AMBA AXI4 Protocol
  • Scalable performance: 1X, 2X, 4X I/O widths.
  • Programmable SPI clock mode of 0 or 3.
  • Programmable serial clock frequency.
  • Optional use of transmit and receive FIFOs with configurable FIFO depth for register-based access only.

Block Diagram

Ordering Information

The QSPI Flash Controller IP Core can be generated and configured in Lattice Propel™ Builder software free of charge.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
QSPI Flash Controller Driver API Reference
FPGA-TN-02339 1.4 6/26/2025 PDF 652.7 KB
QSPI Flash Controller IP User Guide
FPGA-IPUG-02248 1.3 6/26/2025 PDF 2.5 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
QSPI Flash Controller Driver API Reference
FPGA-TN-02339 1.4 6/26/2025 PDF 652.7 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
QSPI Flash Controller IP User Guide
FPGA-IPUG-02248 1.3 6/26/2025 PDF 2.5 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
QSPI Flash Controller IP Release Notes
FPGA-RN-02016 1.1 6/26/2025 PDF 203.2 KB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.