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  • Avant-G Versa Board

    Board

    Avant-G Versa Board

    The Avant-G Versa Board features on-board LPDDR4, PCIe Gen3, and majority of I/O bonded out to FMC, PMOD, SMA and other connectors available.
    Avant-G Versa Board
  • 10Gb Ethernet MAC+PHY IP Core

    IP Core

    10Gb Ethernet MAC+PHY IP Core

    The Lattice 10G Ethernet (GbE) IP core supports the ability to transmit and receive data between a host processor and an Ethernet network.
    10Gb Ethernet MAC+PHY IP Core
  • PCI Express for Avant FPGAs

    IP Core

    PCI Express for Avant FPGAs

    The Lattice PCIe X8 IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
    PCI Express for Avant FPGAs
  • QSPI Flash Controller IP Core

    IP Core

    QSPI Flash Controller IP Core

    The QSPI Flash Controller IP allows communication with multiple external SPI flash devices using standard, extended dual/quad, dual, or quad SPI protocols.
  • RISC-V MC CPU IP Core

    IP Core

    RISC-V MC CPU IP Core

    The Lattice RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC).
    RISC-V MC CPU IP Core
  • RISC-V RX CPU IP Core

    IP Core

    RISC-V RX CPU IP Core

    Lattice RISC-V RX IP processes data and instructions while monitoring the external interrupts, using 32-bit RISC-V processor core and several submodules.
    RISC-V RX CPU IP Core
  • RISC-V SM CPU IP Core

    IP Core

    RISC-V SM CPU IP Core

    Lattice RISC-V SM CPU IP core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.
    RISC-V SM CPU IP Core
  • AHB-Lite to AXI4 Bridge IP Core

    IP Core

    AHB-Lite to AXI4 Bridge IP Core

    The Lattice AHB-Lite to AXI4 Bridge IP Core is used for interfacing one AHB-Lite Manager and one AXI4 Subordinate.
    AHB-Lite to AXI4 Bridge IP Core
  • AXI4 Interconnect Module

    IP Core

    AXI4 Interconnect Module

    AXI4 Interconnect is a flexible, versatile, and easy-to-use IP with high-performance and low-latency interconnect fabric for AMBA 4 AXI/AXI-lite based systems.
    AXI4 Interconnect Module
  • AXI4 Multi Port Bridge for Memory Controller IP Core

    IP Core

    AXI4 Multi Port Bridge for Memory Controller IP Core

    The AXI4 Multi Port Bridge for Memory Controller (MPMC) IP connects multiple external managers to a single memory controller.
    AXI4 Multi Port Bridge for Memory Controller IP Core
  • MIPI CSI-2 to HDMI Demonstration

    Demo

    MIPI CSI-2 to HDMI Demonstration

    Lattice MIPI-HDMI Demonstration is built using multiple Lattice IPs and some additional glue logic necessary to connect the IPs in a processing pipeline.
    MIPI CSI-2 to HDMI Demonstration
  • MIPI CSI-2 to HDMI Reference Design

    Reference Design

    MIPI CSI-2 to HDMI Reference Design

    MIPI CSI-2 to HDMI Reference Design includes the synthesizable MIPI-HDMI core design & stimulus generators, checkers, & a testbench necessary to simulate the design
    MIPI CSI-2 to HDMI Reference Design
  • I3C Controller IP Core

    IP Core

    I3C Controller IP Core

    I3C Controller IP Core is a two-wire, bi-directional serial bus designed for use with many sensor secondary devices controlled by a single I3C controller.
    I3C Controller IP Core
  • I3C Target IP Core

    IP Core

    I3C Target IP Core

    I3C Target IP Core enables greater than 10-fold speed improvements, more effective bus power management, and backward compatibility with I2C devices.
    I3C Target IP Core
  • AXI Register Slice IP Core

    IP Core

    AXI Register Slice IP Core

    The AXI Register Slice connects the AXI subordinate to the AXI manager by introducing pipeline stages in between to close the timing in critical paths.
    AXI Register Slice IP Core
  • Memory Controller IP Core

    IP Core

    Memory Controller IP Core

    The Memory Controller IP reduces the effort required to integrate the LPDDR4 memory controller with the user application design.
    Memory Controller IP Core
  • SPI Flash Memory Controller IP Core

    IP Core

    SPI Flash Memory Controller IP Core

    The SPI Flash Memory Controller IP Core provides an industry-standard interface between a CPU and an off-chip SPI flash memory device.
    SPI Flash Memory Controller IP Core
  • Watchdog Timer IP Core

    IP Core

    Watchdog Timer IP Core

    The Watchdog Timer IP Core is designed for use as an indicator that a corrective action is needed in response to a computer or a processor malfunction.
    Watchdog Timer IP Core
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