The Lattice Semiconductor RISC-V SM CPU IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC). The CPU core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.
The Timer submodule is a 64-bit real time counter, which compares a real-time register with another register to assert the timer interrupt. The PIC submodule aggregates up to eight external interrupt inputs into one external interrupt. The submodule registers are accessed by the processor core using a 32-bit Advanced High-performance Bus - Lite (AHB-L) interface.
The design is implemented in Verilog HDL. It can be configured and generated using the Lattice Propel Builder software. It can be targeted to CrossLink-NX/MachXO3D/MachXO3/MachXO2 FPGA devices and implemented using the Lattice Diamond/Radiant software Place and Route tool integrated with the Synplify Pro synthesis tool.