RISC-V SM CPU IP Core

RISC-V CPU for State Machine Applications

Related Products


Newsletter Subscription

The Lattice Semiconductor RISC-V SM CPU IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC). The CPU core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.

Resource Utilization details are available in the IP Core User Guide.

Features

  • RV32I instruction set
  • Five stages of pipelines
  • Support the AHB-L bus standard for instruction/data port
  • Optional debug through Gnu Debugger (GDB) and Open On-Chip Debugger (OpenOCD)
  • Interrupt and exception handling with Machine mode in RISC-V privileged ISA Specification Revision 1.10

Block Diagram

RISC-V SM CPU IP Core Block DiagramExpand Image

Resource Utilization

Avant Device
Configuration LUTs Registers sysMEM EBRs
Processor core only 1045 570 2
Processor core + PIC 1125 607 2
Processor core + Timer 1347 715 2
Processor core + Debug 1352 997 2
Processor core + PIC + Timer 1443 742 2
Processor core + PIC + Timer + Debug 1730 1118 2

Note: Resource utilization characteristics are generated using Lattice Radiant software.

CertusPro-NX Device
Configuration LUTs Registers sysMEM EBRs
Processor core only 996 570 2
Processor core + PIC 1129 607 2
Processor core + Timer 1369 726 2
Processor core + Debug 1257 947 2
Processor core + PIC + Timer 1466 742 2
Processor core + PIC + Timer + Debug 1652 1119 2

Note: Resource utilization characteristics are generated using Lattice Radiant software.

CrossLink-NX Device
Configuration LUTs Registers sysMEM EBRs
Processor core only 899 596 2
Processor core + PIC 980 615 2
Processor core + Timer 1365 715 2
Processor core + Debug 1233 974 2
Processor core + PIC + Timer 1382 724 2
Processor core + PIC + Timer + Debug 1721 1127 2

Note: Resource utilization characteristics are generated using Lattice Radiant software.

To view the complete Resource Utilization of the RISC-V SM IP Core, click here to view the table.

Ordering Information

The RISC-V SM CPU IP Core is provided at no additional cost with Lattice Propel Builder.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
RISC-V SM CPU IP - Lattice Propel Builder 2024.2 User Guide
FPGA-IPUG-02268 1.0 12/20/2024 PDF 493.2 KB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

ABOUT LATTICE

SALES

SUPPORT

FOLLOW