RISC-V SM CPU IP Core

RISC-V CPU for State Machine Applications

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The Lattice Semiconductor RISC-V SM CPU IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC). The CPU core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.

Resource Utilization details are available in the IP Core User Guide.

Features

  • RV32I instruction set
  • Five stages of pipelines
  • Support the AHB-L bus standard for instruction/data port
  • Optional debug through Gnu Debugger (GDB) and Open On-Chip Debugger (OpenOCD)
  • Interrupt and exception handling with Machine mode in RISC-V privileged ISA Specification Revision 1.10

Block Diagram

RISC-V SM CPU IP Core Block DiagramExpand Image

Ordering Information

The RISC-V SM CPU IP Core is provided at no additional cost with Lattice Propel Builder.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
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RISC-V SM CPU (State Machine) IP Module User Guide - Lattice Propel Builder
FPGA-IPUG-02279 1.0 6/26/2025 PDF 553.8 KB

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