RISC-V SM CPU IP Core

RISC-V CPU for State Machine Applications

The Lattice Semiconductor RISC-V SM CPU IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC). The CPU core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant. The Timer submodule is a 64-bit real time counter, which compares a real-time register with another register to assert the timer interrupt. The PIC submodule aggregates up to eight external interrupt inputs into one external interrupt. The submodule registers are accessed by the processor core using a 32-bit Advanced High-performance Bus – Lite (AHB-L) interface.

The design is implemented using Verilog HDL, and it can be configured and generated using the Lattice Propel™ Builder software. It supports Lattice Avant™, MachXO5™-NX, Certus™-NX, CertusPro™-NX, CrossLink™-NX, MachXO3D™, MachXO3™, and MachXO2™ FPGA devices.

Processing Data and Monitoring External Interrupts Simultaneously - It uses one AHB-L interface (Read-Only) for instruction fetch and another AHB-L interface (Read/Write Access) for data access.

PIC and Timer Submodules - The CPU soft IP contains submodules: PIC and Timer. The PIC and Timer share the same start address in the memory map and a fixed two KB address range is allocated, if either PIC or Timer is enabled.

Features

  • RV32I instruction set
  • Five stages of pipelines
  • Support the AHB-L bus standard for instruction/data port
  • Optional debug through Gnu Debugger (GDB) and Open On-Chip Debugger (OpenOCD)
  • Interrupt and exception handling with Machine mode in RISC-V privileged ISA Specification Revision 1.10

Block Diagram

Resource Utilization

Avant Device
Configuration LUTs Registers sysMEM EBRs
Processor core only 1045 570 2
Processor core + PIC 1125 607 2
Processor core + Timer 1347 715 2
Processor core + Debug 1352 997 2
Processor core + PIC + Timer 1443 742 2
Processor core + PIC + Timer + Debug 1730 1118 2

Note: Resource utilization characteristics are generated using Lattice Radiant software.

CertusPro-NX Device
Configuration LUTs Registers sysMEM EBRs
Processor core only 996 570 2
Processor core + PIC 1129 607 2
Processor core + Timer 1369 726 2
Processor core + Debug 1257 947 2
Processor core + PIC + Timer 1466 742 2
Processor core + PIC + Timer + Debug 1652 1119 2

Note: Resource utilization characteristics are generated using Lattice Radiant software.

CrossLink-NX Device
Configuration LUTs Registers sysMEM EBRs
Processor core only 899 596 2
Processor core + PIC 980 615 2
Processor core + Timer 1365 715 2
Processor core + Debug 1233 974 2
Processor core + PIC + Timer 1382 724 2
Processor core + PIC + Timer + Debug 1721 1127 2

Note: Resource utilization characteristics are generated using Lattice Radiant software.

To view the complete Resource Utilization of the RISC-V SM IP Core, click here to view the table.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
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RISC-V SM CPU IP Core - User Guide
FPGA-IPUG-02240 1.0 12/5/2023 PDF 577.5 KB

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