RISC-V MC CPU IP Core

RISC-V CPU for Micro-controller Applications

The Lattice Semiconductor RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC). The CPU core is with instruction and data caches. The CPU core supports RV32IMC instruction set, external interrupts, and debug feature that is JTAG – IEEE 1149.1 compliant. The Timer submodule is a 64-bit real time counter, which compares a real-time register with another register to assert the timer interrupt. The PIC submodule aggregates up to eight external interrupt inputs into one external interrupt. The submodule registers are accessed by the processor core using a 32-bit Advanced High-performance Bus – Lite (AHB-L) interface.

The design is implemented using Verilog HDL, and it can be configured and generated using the Lattice Propel™ Builder software. It supports Lattice Avant™, MachXO5™-NX, Certus™-NX, CertusPro™-NX, CrossLink™-NX, MachXO3D™, MachXO3™, and MachXO2™ FPGA devices.

Features

  • RV32I[MC] instruction set and Five stages of pipelines
  • Support the AHB-L bus standard for instruction/data port
  • Optional debug through GDB and OpenOCD; and optional Timer/PIC modules
  • Interrupt and exception handling with Machine mode in RISC-V privileged ISA Specification v1.10
  • Optional caches, including a 4 KB two-way instruction cache and a 4 KB two-way data cache (for Avant, MachXO5-NX, Certus-NX, CertusPro-NX, and CrossLink-NX only)

Block Diagram

Resource Utilization

Resource Utilization in CrossLink-NX Device (with Cache Disabled)
Configuration LUTs Registers EBRs DSPs
Processor core only 1620 821 2 0
Processor core + PIC 1789 859 2 0
Processor core + Timer 2103 959 2 0
Processor core + Debug 1979 1194 2 0
Processor core + C_EXT 1911 830 2 0
Processor core + C_EXT + M_EXT 2417 1172 2 6
Processor core + PIC + Timer 2226 994 2 0
Processor core + PIC + Timer + Debug 2494 1375 2 0
Processor core + PIC + Timer + Debug + C_EXT 2790 1450 2 0

Note: Resource utilization characteristics are generated using Lattice Radiant software.

Resource Utilization in CrossLink-NX Device (with Cache Enabled)
Configuration LUTs Registers EBRs DSPs
Processor core only 3372 1423 16 0
Processor core + PIC 3568 1479 16 0
Processor core + Timer 3753 1574 16 0
Processor core + Debug 3687 1810 16 0
Processor core + C_EXT 3711 1551 16 0
Processor core + C_EXT + M_EXT 4133 1879 16 6
Processor core + PIC + Timer 3894 1606 16 0
Processor core + PIC + Timer + Debug 4309 1980 16 0
Processor core + PIC + Timer + Debug + C_EXT 4568 2032 16 0

Note: Resource utilization characteristics are generated using Lattice Radiant software.

Resource Utilization in MachXO3D Device (with Cache Disabled)
Configuration LUTs Registers EBRs
Processor core only 1450 806 4
Processor core + PIC 1559 845 4
Processor core + Timer 1844 955 4
Processor core + Debug 1726 1108 4
Processor core + C_EXT 1738 860 4
Processor core + PIC + Timer 1927 989 4
Processor core + PIC + Timer + Debug 2162 1287 4
Processor core + PIC + Timer + Debug + C_EXT 2385 1345 4

Note: Resource utilization characteristics are generated using Lattice Diamond software.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
RISC-V MC CPU IP - Lattice Propel Builder 2.0
FPGA-IPUG-02157 1.0 5/11/2021 PDF 1.1 MB
Small-sized RISC-V CPU IP Core- Lattice Propel Builder
FPGA-IPUG-02114 1.0 6/3/2020 PDF 1.4 MB
RISC-V MC CPU IP - Lattice Propel Builder
FPGA-IPUG-02210 1.0 10/31/2022 PDF 523.8 KB

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