RISC-V MC CPU IP核

RISC-V CPU用于微控制器应用

莱迪思半导体的RISC-V MC CPU软IP包括了一个32位的RISC-V处理器核和可选的子模块——定时器和可编程中断控制器(PIC)。CPU核支持RV32I指令集、外部中断和调试功能,符合JTAG–IEEE 1149.1标准。

定时器子模块是一个64位实时计数器,它将实时寄存器与另一个寄存器进行比较以触发定时器中断。PIC子模块最多将八个外部中断输入聚合为一个外部中断。处理器核通过使用32位AHB-L接口访问子模块寄存器。

该设计通过Verilog HDL实现。它可以通过莱迪思Propel Builder软件进行配置和生成。它可用于CrossLink-NX和MachXO3D FPGA器件,并通过集成了Synplify Pro综合工具的莱迪思Radiant或Diamond软件布局布线工具实现。

特性

  • RV32I指令集(仅当未勾选PFR_OPT时RV32C才有效)
  • 五级流水线
  • 支持用于指令/数据端口的AHB-L总线标准
  • 通过GDB和OpenOCD实现可选调试
  • 可选的定时器/ PIC模块
  • 使用RISC-V特权级ISA规范v1.10的机器模式进行中断和异常处理
Lattice Propel

Block Diagram

Resource Utilization

Lattice Avant Device (with Cache Disabled)
Configuration LUTs Registers EBRs DSPs
Processor core only 2015 867 2 0
Processor core + PIC 2097 886 2 0
Processor core + Timer 2456 979 2 0
Processor core + Debug 2376 1268 2 0
Processor core + C_EXT 2202 860 2 0
Processor core + C_EXT + M_EXT 2731 1284 2 6
Processor core + PIC + Timer 2535 1017 2 0
Processor core + PIC + Timer + Debug 2869 1444 2 0
Processor core + PIC + Timer + Debug + C_EXT 3128 1528 2 0

Note: Resource utilization characteristics are generated using Lattice Radiant software.

Lattice Avant Device (with Cache Enabled)
Configuration LUTs Registers EBRs DSPs
Processor core only 3340 1364 18 0
Processor core + PIC 3437 1406 18 0
Processor core + Timer 3857 1548 18 0
Processor core + Debug 3708 1806 18 0
Processor core + C_EXT 3671 1546 18 0
Processor core + C_EXT + M_EXT 4431 1861 18 6
Processor core + PIC + Timer 3809 1655 18 0
Processor core + PIC + Timer + Debug 4381 1995 18 0
Processor core + PIC + Timer + Debug + C_EXT 4559 2168 18 0

Note: Resource utilization characteristics are generated using Lattice Radiant software.

CertusPro-NX Device (with Cache Disabled)
Configuration LUTs Registers EBRs DSPs
Processor core only 1978 834 2 0
Processor core + PIC 2105 886 2 0
Processor core + Timer 2446 990 2 0
Processor core + Debug 2304 1218 2 0
Processor core + C_EXT 2288 896 2 0
Processor core + C_EXT + M_EXT 2790 1185 2 6
Processor core + PIC + Timer 2578 1032 2 0
Processor core + PIC + Timer + Debug 2871 1390 2 0
Processor core + PIC + Timer + Debug + C_EXT 3220 1461 2 0

Note: Resource utilization characteristics are generated using Lattice Radiant software.

CertusPro-NX Device (with Cache Enabled)
Configuration LUTs Registers EBRs DSPs
Processor core only 3031 1461 20 0
Processor core + PIC 3391 1505 20 0
Processor core + Timer 3812 1607 20 0
Processor core + Debug 3667 1854 20 0
Processor core + C_EXT 3691 1613 19 0
Processor core + C_EXT + M_EXT 4334 2007 19 6
Processor core + PIC + Timer 3926 1671 20 0
Processor core + PIC + Timer + Debug 4139 2012 20 0
Processor core + PIC + Timer + Debug + C_EXT 4450 2169 19 0

Note: Resource utilization characteristics are generated using Lattice Radiant software.

To view the complete Resource Utilization of the RISC-V MC IP Core, click here to view the table.

文档

快速参考
标题 编号 版本 日期 格式 文件大小
选择全部
RISC-V MC CPU IP Core - User Guide
FPGA-IPUG-02239 1.0 12/5/2023 PDF 550.4 KB
Small-sized RISC-V CPU IP Core- Lattice Propel Builder
FPGA-IPUG-02114 1.0 6/3/2020 PDF 1.4 MB