The Lattice Semiconductor RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC). The CPU core is with instruction and data caches. The CPU core supports RV32IMC instruction set, external interrupts, and debug feature that is JTAG – IEEE 1149.1 compliant. The Timer submodule is a 64-bit real time counter, which compares a real-time register with another register to assert the timer interrupt. The PIC submodule aggregates up to eight external interrupt inputs into one external interrupt. The submodule registers are accessed by the processor core using a 32-bit Advanced High-performance Bus – Lite (AHB-L) interface.
The design is implemented using Verilog HDL, and it can be configured and generated using the Lattice Propel™ Builder software. It supports Lattice Avant™, MachXO5™-NX, Certus™-NX, CertusPro™-NX, CrossLink™-NX, MachXO3D™, MachXO3™, and MachXO2™ FPGA devices.
Processing Data and Monitoring External Interrupts Simultaneously - It uses one AHB-L interface (Read-Only) for instruction fetch and another AHB-L interface (Read/Write Access) for data access.
PIC and Timer Submodules - The CPU soft IP contains submodules: PIC and Timer. The PIC and Timer share the same start address in the memory map and a fixed two KB address range is allocated, if either PIC or Timer is enabled.