5G Ethernet IP Core

High-performance 5Gb Ethernet for Seamless Ethernet data transmission

Related Products

The Lattice Semiconductor 5G Ethernet IP core supports the ability to transmit and receive data between a host processor and an Ethernet network. The 5G IP core consists of the 10-Gigabit Media Independent Interface (XGMII), which connects media access controllers (MACs) and Physical Layer devices (PHYs). The main function of the 5Gb MAC is to ensure that the media access rules specified in the IEEE 802.3 standards are met while transmitting a frame of data over an Ethernet.

Resource Utilization details are available in the IP Core User Guide

Features

  • MAC
    • Compliant to the IEEE 802.3-2022 standard
    • Supports standard 5 Gbps Ethernet link layer data rate
    • 32-bit AXI4-Stream interface on the client’s transmit and receive interfaces operating at 156.25 MHz
    • 64-bit XGMII interface operating at 78.125 MHz
    • Supports deficit idle count (DIC)
    • Supports VLAN and Jumbo frames of 9,600 bytes
  • PHY
    • Designed to the IEEE 802.3-2022 5GBASE-R specification
    • 64b/66b encoding and decoding
    • XGMII interface: 64-bit, 78.125 MHz
    • Supports AXI4-Lite and management data input/output for PCS
    • TX phase compensation FIFO and RX clock compensation FIFO
    • Supports APB and AXI4-Lite management bus interfaces for control and status register access

Block Diagram

5G-Internet - GraphicsExpand Image

5G Ethernet - Block Diagram

Ordering Information

The 5G Ethernet IP Core is available with the Lattice Radiant Subscription software. To purchase the Lattice Radiant Subscription license, contact Lattice Sales or go to the Lattice Online Store.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
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5G Ethernet IP Core - User Guide
FPGA-IPUG-02313 1.1 7/13/2026 PDF 5.1 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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5G Ethernet IP Core - Release Notes
FPGA-RN-02102 1.1 7/13/2026 PDF 303.2 KB

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