5G Ethernet IP Core

High-performance 5Gb Ethernet for Seamless Ethernet data transmission

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The Lattice Semiconductor 5G Ethernet (GbE) IP core supports the ability to transmit and receive data between a host processor and an Ethernet network. The 5GbE IP core consists of the 10-Gigabit Media Independent Interface (XGMII), which connects media access controllers (MACs) and Physical Layer devices (PHYs). The main function of the 5GbE MAC is to ensure that the media access rules specified in the IEEE 802.3 standards are met while transmitting a frame of data over an Ethernet.

Resource Utilization details are available in the IP Core User Guide

Features

  • MAC
    • Compliant to the IEEE 802.3-2022 standard
    • Supports standard 5 Gbps Ethernet link layer data rate
    • 32-bit AXI4-Stream interface on the client’s transmit and receive interfaces operating at 156.25 MHz
    • 64-bit XGMII interface operating at 78.125 MHz
    • Supports deficit idle count (DIC)
    • Supports VLAN and Jumbo frames of 9,600 bytes
  • PHY
    • Designed to the IEEE 802.3-2022 5GBASE-R specification
    • 64b/66b encoding and decoding
    • XGMII interface: 64-bit, 78.125 MHz
    • Supports AXI4-Lite and management data input/output for PCS
    • TX phase compensation FIFO and RX clock compensation FIFO

Block Diagram

5G Ethernet - Block Diagram

订购信息

  料号
器件系列 单机年度许可 站点永久许可
CertusPro-NX VIDEO-SCALER-CPNX-US VIDEO-SCALER-CPNX-UT
Certus-NX VIDEO-SCALER-CTNX-US VIDEO-SCALER-CTNX-UT
CrossLink-NX VIDEO-SCALER-CNX-US VIDEO-SCALER-CNX-UT

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Documentation

快速参考
资讯资源
标题 编号 版本 日期 格式 文件大小
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5G Ethernet IP Core - User Guide
FPGA-IPUG-02313 1.0 12/11/2025
标题 编号 版本 日期 格式 文件大小
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5G Ethernet IP Core - Release Notes
FPGA-RN-02102 1.0 12/11/2025