PCI Express for Avant FPGAs

Flexible, High-Performance, Easy-to-use Transaction Layer Interface to the PCI Express Bus

PCI Express® is a high performance, fully scalable, and well-defined standard for a wide variety of computing and communications platforms. As a packet-based serial technology, the PCI Express standard greatly reduces the number of required pins and simplifies board routing and manufacturing. PCI Express is a point-to-point technology, as opposed to the multi-drop bus in PCI. Each PCI Express device has the advantage of full duplex communication with its link partner to greatly increase overall system bandwidth. The basic data rate for a single lane is double that of the 32-bit/33 MHz PCI bus. A four-lane link has eight times the data rate in each direction of a conventional bus.

The Lattice PCIe X8 IP Core implementation is a hardened IP with soft logic provided for interface conversion options. The hardened IP is an integration of PHY and Link Layer blocks.

The Lattice PCIe X8 IP Core is supported in the Lattice Avant™-G and Lattice Avant™-X FPGA device family and is available in the Lattice Radiant™ software.

Flexible, High-performance, Easy-to-use Transaction Layer Interface – The Lattice PCIe X8 IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.

PCI Express Base Specification Revision 4.0 Compliant – Hard IP Link Layer key features include PCI Express Base Specification Revision 4.0 compliant including compliance with earlier PCI Express Specifications.

x8 PCI Express Lanes with Support for Bifurcation - Supported lane configurations:
• 1x8 (2024), 1×4, 1×2, 1×1

Features

  • Backward compatible with PCI Express 4.x (2024), 3.x (2024), 2.x, 1.x
  • 16.0GT/s (2024), 8.0GT/s (2024), 5.0 GT/s and 2.5 GT/s line rate support
  • Comprehensive application support: Endpoint and Root Port (2024)
  • With built in DMA capability (2024) and AXI interface
  • Multi-Function support up to 8 Physical Functions and 24 Virtual Functions

Jump to

Block Diagram

Resource Utilization

The resource utilization reports are generated with the Lattice Radiant tool version 3.2 and with PCIe IP core version 2.2.0.2 generated for the following parameter settings:

  • Maximum Payload size = 256 Bytes
  • BAR0 Enabled with memory size = 64 kB
  • Ref Clk = 100 MHz

Lattice PCIe X8 IP Core on LAV-AT-500G-1LI with various link widths:

PCIe Core Config Device Family Map Resource Utilization
DMA Non-DMA
LUT4 PFU Register I/O Buffer EBR LUT4 PFU Register I/O Buffer EBR Data Interface Type
1×1/2×1/3×1 EP Avant-G/X - - - - 864 684 0 4 AXI4_STREAM
1×2/2×2/3×2 EP Avant-G/X - - - - 1136 874 0 6 AXI4_STREAM
1×4/2×4/3×4 EP Avant-G/X - - - - 1628 1284 0 12 AXI4_STREAM
x1/x2/x3 EP Avant-G/X - - - - 0 3 0 0 TLP

Ordering Information

  Part Number
Device Family Multi-site Perpetual Single Seat Annual
Avant-G PCI-EXP8-AVG-UT
PCI-EXP4-AVG-UT
PCI-EXP2-AVG-UT
PCI-EXP8-AVG-US
PCI-EXP4-AVG-UT
PCI-EXP2-AVG-UT
Avant-X PCI-EXP8-AVX-UT
PCI-EXP4-AVX-UT
PCI-EXP2-AVX-UT
PCI-EXP8-AVG-UT
PCI-EXP4-AVG-UT
PCI-EXP2-AVG-UT

OPN Reference Guide

PCI-EXP8: covers x1, x2, x4 and x8
PCI-EXP4: covers x1, x2 and x4
PCI-EXP2: covers x1 and x2

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
PCI Express X8 IP Core - Lattice Radiant Software
FPGA-IPUG-02243 1.0 1/5/2024 PDF 3.4 MB

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