PCI Express for Avant FPGAs

Flexible, High-Performance, Easy-to-use Transaction Layer Interface to the PCI Express Bus

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The Lattice PCIe x8 IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus. Its implementation is a hardened IP with soft logic provided for interface conversion options. The hardened IP is an integration of PHY and Link Layer blocks. The Lattice PCIe x8 IP Core is supported in the Lattice Avant-G and Lattice Avant-X FPGA device family and is available in the Lattice Radiant™ software.

Resource Utilization details are available in the IP Core User Guide.

The Hard IP PHY key features include:

  • Aggregation and bifurcation up to x4 lanes and x8 lanes PHY configuration
  • Data rates of 2.5 Gbps, 5.0 Gbps, 8.0 Gbps, and 16.0 Gbps
  • Selectable parallel data widths such as 8, 16, 32, 64
  • 8b/10b encoding at 2.5 Gbps and 5 Gbps, and 128b/130b encoding at 8 Gbps and 16 Gbps

The Hard IP Link Layer key features include:

  • PCI Express Base Specification Revision 4.0 compliant including compliance with earlier PCI Express Specifications.
  • Backward compatible with PCI Express 3.x, 2.x, 1.x
  • x8 PCI Express Lanes with support for bifurcation. Supported lane configurations:
    • Radiant 2023.2 – 1 × 4, 1 × 2, 1 × 1
    • Radiant 2024.1 and future Radiant releases – 1 × 8, 1 × 4, 1 × 2, 1 × 1
  • 16.0GT/s, 8.0GT/s, 5.0 GT/s, and 2.5 GT/s line rate support

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Block Diagram

PCI Express for Avant FPGAs Block DiagramExpand Image

Resource Utilization

The resource utilization reports are generated with the Lattice Radiant tool version 3.2 and with PCIe IP core version 2.2.0.2 generated for the following parameter settings:

  • Maximum Payload size = 256 Bytes
  • BAR0 Enabled with memory size = 64 kB
  • Ref Clk = 100 MHz

Lattice PCIe X8 IP Core on LAV-AT-500G-1LI with various link widths:

PCIe Core Config Device Family Map Resource Utilization
DMA Non-DMA
LUT4 PFU Register I/O Buffer EBR LUT4 PFU Register I/O Buffer EBR Data Interface Type
1×1/2×1/3×1 EP Avant-G/X - - - - 864 684 0 4 AXI4_STREAM
1×2/2×2/3×2 EP Avant-G/X - - - - 1136 874 0 6 AXI4_STREAM
1×4/2×4/3×4 EP Avant-G/X - - - - 1628 1284 0 12 AXI4_STREAM
x1/x2/x3 EP Avant-G/X - - - - 0 3 0 0 TLP

Ordering Information

  Part Number
Device Family Multi-site Perpetual Single Seat Annual
Avant-G PCI-EXP8-AVG-UT
PCI-EXP4-AVG-UT
PCI-EXP2-AVG-UT		 PCI-EXP8-AVG-US
PCI-EXP4-AVG-UT
PCI-EXP2-AVG-UT
Avant-X PCI-EXP8-AVX-UT
PCI-EXP4-AVX-UT
PCI-EXP2-AVX-UT		 PCI-EXP8-AVG-UT
PCI-EXP4-AVG-UT
PCI-EXP2-AVG-UT

OPN Reference Guide

PCI-EXP8: covers x1, x2, x4 and x8
PCI-EXP4: covers x1, x2 and x4
PCI-EXP2: covers x1 and x2

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
PCIe x8 IP Core User Guide
FPGA-IPUG-02243 1.2 12/20/2024 PDF 5.1 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
PCIe x8 IP Release Notes
FPGA-RN-02061 1.0 12/20/2024 PDF 206.4 KB

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