The Lattice PCIe x8 IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus. The Lattice PCIe x8 IP Core implementation is a hardened IP with soft logic provided for interface conversion options. The hardened IP is an integration of PHY and Link Layer blocks.
Resource Utilization details are available in the IP Core User Guide.
The Hard IP PHY key features include:
- Aggregation and bifurcation up to x4 lanes and x8 lanes PHY configuration
- 8b/10b encoding at 2.5 GT/s and 5 GT/s, and 128b/130b encoding at 8 GT/s and 16 GT/s
- Adaptive and configurable RX Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalizer (DFE)
- Adaptive and programmable TX equalization
The Hard IP Link Layer key features include:
- PCI Express Base Specification Revision 4.0 compliant including compliance with earlier PCI Express Specifications.
- Backward compatible with PCI Express 3.x, 2.x, 1.x
- Comprehensive application support: Endpoint, Root Port (future release)
- Multi-function support per link: PCIe x8 capable Core supports 1-8 PF
