The Lattice Semiconductor Fast Fourier Transform (FFT) Compiler IP Core offers forward and inverse FFTs for point sizes from 64 to 16384. The FFT Compiler IP Core can be configured to perform forward FFT, inverse FFT (IFFT), or port selectable forward/inverse FFT. It offers two modes of implementation: High Performance (Streaming I/O) and Low Resource (Burst I/O). In High Performance implementation, the FFT Compiler IP Core can perform real-time computations with continuous data streaming in and out at clock rate. There can also be arbitrary gaps between data blocks allowing discontinuous data blocks.
In Low Resource implementation, the requirement is to use less slice (logic unit of Lattice FPGA devices), Embedded Block RAM (EBR), and Digital Signal Processor (DSP) resources. The device could also be too small to accommodate the High-Performance version.
Allows Several Different Modes - To account for the data growth in fine register length implementations, the FFT Compiler IP Core allows several different modes (fixed and dynamic) for scaling data after each radix-2 stage of the FFT computation.
Increased Dynamic Range for Intermediate Computations - The Low Resource version also supports block floating point arithmetic that provides increased dynamic range for intermediate computations. It allows the number of FFT points to be varied dynamically through a port.