FFT Compiler IP Core

Offers Two Implementation Modes: High Performance (Streaming I/O) and Low Resource (Burst I/O)

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The Lattice Semiconductor Fast Fourier Transform (FFT) Compiler IP Core offers forward and inverse FFTs for point sizes from 64 to 16384. The FFT Compiler IP Core can be configured to perform forward FFT, inverse FFT (IFFT), or port selectable forward/inverse FFT. It offers two modes of implementation: High Performance (Streaming I/O) and Low Resource (Burst I/O). In High Performance implementation, the FFT Compiler IP Core can perform real-time computations with continuous data streaming in and out at clock rate. There can also be arbitrary gaps between data blocks allowing discontinuous data blocks.

In Low Resource implementation, the requirement is to use less slice (logic unit of Lattice FPGA devices), Embedded Block RAM (EBR), and Digital Signal Processor (DSP) resources. The device could also be too small to accommodate the High-Performance version.

Allows Several Different Modes - To account for the data growth in fine register length implementations, the FFT Compiler IP Core allows several different modes (fixed and dynamic) for scaling data after each radix-2 stage of the FFT computation.

Increased Dynamic Range for Intermediate Computations - The Low Resource version also supports block floating point arithmetic that provides increased dynamic range for intermediate computations. It allows the number of FFT points to be varied dynamically through a port.

Features

  • Wide range of point sizes: 64, 128, 256, 512, 1024, 2048, 4096, 8192, and 16384
  • Choice of high-performance (streaming I/O) or Low Resource (burst I/O) versions
  • Run-time variable FFT point size
  • Forward, inverse, or port-configurable forward/inverse transform modes
  • Choice of no scaling, fixed scaling (RS111/RS211), or dynamically variable stage-wise scaling

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Block Diagram

FFT CompilerExpand Image

Resource Utilization

Avant Family
LAV-AT-500E-1LFG1156I
Configuration Clk Fmax (MHz)1 Registers LUTs EBR DSPs
Default 251.762 830 638 3.0 4
Architecture: High Performance,
Others = Default 		- - - - -
Architecture: High Performance,
Multiplier Type: LUT-based		 156.323 1674 4021 1.0 0
FFT Mode: Dynamic Through Port,
Others = Default		 251.762 835 639 3.0 4
Input Data Width: 24,
Twiddle Factor Width: 24,
Others = Default		 185.632 1921 1156 3.0 16
Multiplier Type: LUT-based,
Memory Type: Distributed Memory,
Others = Default		 178.508 1296 2163 0 0

Note:
1. Fmax is generated when the FPGA design only contains FFT Compiler IP Core, and the target frequency is 100MHz. These values may be reduced when user logic is added to the FPGA design

LAV-AT-500E-1LFG1156I
Configuration Clk Fmax (MHz)1 Registers LUTs EBR DSPs
Default 225.887 830 638 3.0 4
Architecture: High Performance,
Others = Default 		- - - - -
Architecture: High Performance,
Multiplier Type: LUT-based		 145.815 1674 4021 1.0 0
FFT Mode: Dynamic Through Port,
Others = Default		 237.304 835 639 3.0 4
Input Data Width: 24,
Twiddle Factor Width: 24,
Others = Default		 162.655 1921 1156 3.0 16
Multiplier Type: LUT-based,
Memory Type: Distributed Memory,
Others = Default		 165.673 1296 2163 0 0

Note:
1. Fmax is generated when the FPGA design only contains FFT Compiler IP Core, and the target frequency is 100MHz. These values may be reduced when user logic is added to the FPGA design

Nexus Family
LFMXO5-25-9BBG400I
Configuration Clk Fmax (MHz)1 Registers LUTs EBR DSPs2
Default 200 999 673 3 4
Architecture: High Performance,
Others = Default 		200 1128 1527 1 8
Architecture: High Performance,
Multiplier Type: LUT-based		 131.631 2338 4343 1 0
FFT Mode: Dynamic Through Port,
Others = Default		 200 1004 674 3 4
Input Data Width: 24,
Twiddle Factor Width: 24,
Others = Default		 200 1483 973 6 16
Multiplier Type: LUT-based,
Memory Type: Distributed Memory,
Others = Default		 140.154 1280 2364 0 0

Notes:
1. Fmax is generated when the FPGA design only contains FFT Compiler IP Core, and the target frequency is 100MHz. These values may be reduced when user logic is added to the FPGA design.
2. Number of Multipliers

LFMXO5-25-7BBG400I
Configuration Clk Fmax (MHz)1 Registers LUTs EBR DSPs2
Default 164.772 999 673 3 4
Architecture: High Performance,
Others = Default 		167.757 1128 1527 1 8
Architecture: High Performance,
Multiplier Type: LUT-based		 84.402 2110 4349 1 0
FFT Mode: Dynamic Through Port,
Others = Default		 171.527 1004 674 3 4
Input Data Width: 24,
Twiddle Factor Width: 24,
Others = Default		 162.153 1483 973 6 16
Multiplier Type: LUT-based,
Memory Type: Distributed Memory,
Others = Default		 85.121 1280 2364 0 0

Notes:
1. Fmax is generated when the FPGA design only contains FFT Compiler IP Core, and the target frequency is 100MHz. These values may be reduced when user logic is added to the FPGA design.
2. Number of Multipliers

To view the complete Resource Utilization of the FFT Compiler IP Core, click here to view the datasheet.

Ordering Information

Device Family Part Number
Multi-site Perpetual Single Machine Annual
Avant-G FFT-COMP-AVG-UT FFT-COMP-AVG-US
Avant-X FFT-COMP-AVX-UT FFT-COMP-AVX-US
Avant-E FFT-COMP-AVE-UT FFT-COMP-AVE-US
MachXO5-NX FFT-COMP-XO5-UT FFT-COMP-XO5-US
CertusPro-NX FFT-COMP-CPNX-UT FFT-COMP-CPNX-US
CrossLink-NX FFT-COMP-CNX-UT FFT-COMP-CNX-US
Certus-NX FFT-COMP-CTNX-UT FFT-COMP-CTNX-US
ECP5 FFT-COMP-E5-UT FFT-COMP-E5-US
LatticeECP3 FFT-COMP-E3-UT2 FFT-COMP-E3-US
LatticeECP2M FFT-COMP-PM-UT2 -
LatticeECP2 FFT-COMP-P2-UT2 -
LatticeEC/ECP FFT-COMP-E2-UT2 -
LatticeXP2 FFT-COMP-X2-UT2 -
LatticeECP FFT-COMP-EP-UT1 -

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

To find out how to purchase the FFT Compiler IP core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
FFT Compiler IP Core - Lattice Radiant Software
FPGA-IPUG-02153 1.4 6/5/2023 PDF 1.1 MB
FFT Compiler IP Core - User Guide
FPGA-IPUG-02045 2.2 10/1/2023 PDF 1.4 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
IPexpress Quick Start Guide
8/5/2010 PDF 304.8 KB

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