The Lattice Semiconductor RISC-V Nano CPU IP contains a 32-bit RISC-V processor core and a lightweight interrupt merge controller. The CPU core supports the RV32I instruction set and external interrupt. The interrupt controller submodule aggregates up to four external interrupt inputs into one external interrupt.
Features
- RV32I instruction set
- Supports the AHB-L bus standard for instruction/data ports
- Lightweight interrupt merge controller module
- Interrupt and exception handling with the Machine mode in RISC-V privileged ISA Specification Revision 1.10
