RISC-V Nano CPU IP Core

32-bit RISC-V Processor Core with a Lightweight Interrupt

Lattice Semiconductor RISC-V Nano CPU IP contains a 32-bit RISC-V processor core and a lightweight interrupt merge controller. The CPU core supports the RV32I instruction set and external interrupt. The interrupt controller submodule aggregates up to four external interrupt inputs into one external interrupt.

The design is implemented using Verilog HDL, and it can be configured and generated using the Lattice Propel™ Builder software. It supports iCE40 UltraPlus™, Lattice Avant™, MachXO5™-NX, CrossLink™-NX, Certus™-NX, CertusPro™-NX, MachXO3D™, MachXO3™, and MachXO2™ FPGA devices.

Resource Utilization details are available in the RISC-V Nano CPU User Guide.

Features

  • RV32I instruction set
  • Five stage pipeline
  • Supports the AHB-L bus standard for instruction/data ports
  • Lightweight interrupt merge controller module
  • Interrupt and exception handling with the Machine mode in RISC-V privileged ISA Specification Revision 1.10

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Block Diagram

Ordering Information

The RISC-V Nano CPU IP Core is provided at no additional cost with Lattice Propel Builder.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
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RISC-V Nano CPU IP - Lattice Propel Builder 2024.2 User Guide
FPGA-IPUG-02271 1.0 12/20/2024 PDF 362.4 KB

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