Lattice Semiconductor RISC-V Nano CPU IP contains a 32-bit RISC-V processor core and a lightweight interrupt merge controller. The CPU core supports the RV32I instruction set and external interrupt. The interrupt controller submodule aggregates up to four external interrupt inputs into one external interrupt.
The design is implemented using Verilog HDL, and it can be configured and generated using the Lattice Propel™ Builder software. It supports iCE40 UltraPlus™, Lattice Avant™, MachXO5™-NX, CrossLink™-NX, Certus™-NX, CertusPro™-NX, MachXO3D™, MachXO3™, and MachXO2™ FPGA devices.
Resource Utilization details are available in the RISC-V Nano CPU User Guide.