RISC-V Nano CPU IP Core

32-bit RISC-V Processor Core with a Lightweight Interrupt

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The Lattice Semiconductor RISC-V Nano CPU IP contains a 32-bit RISC-V processor core and a lightweight interrupt merge controller. The CPU core supports the RV32I instruction set and external interrupt. The interrupt controller submodule aggregates up to four external interrupt inputs into one external interrupt.

Features

  • RV32I instruction set
  • Five stage pipeline
  • Supports the AHB-L bus standard for instruction/data ports
  • Lightweight interrupt merge controller module
  • Interrupt and exception handling with the Machine mode in RISC-V privileged ISA Specification Revision 1.10

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Block Diagram

RISC-V MC放大图片

Ordering Information

The RISC-V Nano CPU IP Core is provided at no additional cost with Lattice Propel Builder.

Documentation

快速参考
标题 编号 版本 日期 格式 文件大小
选择全部
RISC-V Nano CPU IP - Lattice Propel Builder 2025.2 User Guide
FPGA-IPUG-02304 1.0 12/11/2025 PDF 493.6 KB
标题 编号 版本 日期 格式 文件大小
选择全部
RISC-V Nano CPU IP - Lattice Propel Builder 2025.2 User Guide
FPGA-IPUG-02304 1.0 12/11/2025 PDF 493.6 KB

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