MPESTI Initiator Reference Design

Broadcast Power Break Command to All Connecting MPESTI Targets

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The Modular-Peripheral Sideband Tunneling Interface (MPESTI) Initiator Reference Design provides the solution template that uses the MPESTI Initiator IP core, Initiator pattern generator block, and MPESTI Target test component, which is compliant to the MPESTI Base Specification (part of the DC-MHS version 1.0 specification).

To use this Reference Design, ensure that you are using Propel version 2022.1 or Radiant version 2022.1 and beyond, and installed the Propel 2021.1 patch.

MPESTI Initiator IP Core and MPESTI Target Test Components – A communicate with half-duplex bidirectional UART protocol at 250k BAUD rate, 8-bit data, 1-bit odd parity, 1 start bit and 1 stop bit (MPESTI line).

Features

  • Supports one-master-to-many-slaves mode
  • Supports Static Discovery payload with CRC-8 payload checksum
  • Supports Target reset at any time and fault handling such as RX timeout
  • Supports auto trigger Static Discovery Payload request command to all Targets on round robin manner during Discovery phase
  • Supports APB collector interface (slave) to communicate with DC-SCM LTPI IP core and transfer data to DC-SCM module

Jump to

Block Diagram

MPESTI Initiator Reference Design Block DiagramExpand Image

Resource Utilization

MachXO5-NX Resource Usage
LUT4 Registers Oscillator EBR I/O Buffers GSR
1991 1244 0 6 35 1

Documentation

Technical Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
MPESTI Initiator Reference Design – User Guide
FPGA-RD-02274 1.2 11/16/2023 PDF 926.2 KB
MPESTI Initiator Reference Design – Source Code
9/26/2023 ZIP 20.4 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
MPESTI Initiator Reference Design Propel 2022.1 Patch
9/14/2023 EXE 31.2 MB

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