MPESTI Initiator Reference Design

Broadcast Power Break Command to All Connecting MPESTI Targets

M-PESTI is a generic and extensible 1-wire, bidirectional circuit and protocol for applications such as cabled high-speed I/O interposers, managed power distribution, cooling systems, and other sensors. This reference design aims to provide M-PESTI as a peripheral that can be interfaced with an external I2C Controller.

This version of the M-PESTI Initiator Reference Design provides a Lattice Propel solution template that uses the M-PESTI Initiator IP core with an external I2C driver reference code and M-PESTI Target test component. The reference design is compliant with the M-PESTI Base Specification (part of the DC-MHS version 1.0 specification). The Reference Design includes the following collaterals:

  • The SoC design project on which you can view, open, and modify the design through the Lattice Propel™ Builder software. The bitstream can be generated using the Lattice Diamond™ software or Lattice Radiant™ software 
  • The CPLD demonstration bitstream

To learn more about this product design and if you need the old source code, please Submit a Technical Support Case Ticket

Features

  • Communicates via half-duplex bidirectional UART protocol at 250k baud rate, 8-bit data, 1-bit odd parity, 1 stop bit, and 1 stop bit on to the M-PESTI port
  • Supports Static Discovery payload with CRC-8 payload checks
  • Supports one initiator to many targets system
  • Supports a configurable number of M-PESTI devices, up to 64 targets
  • Supports round-robin autonomous Static Discovery Payload request commands during the discovery phase, round-robin autonomous Virtual Wire Exchange during the active phase, and broadcast commands to all targets simultaneously

Block Diagram

Documentation

Technical Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
MPESTI Initiator Reference Design – Source Code
5/14/2026 ZIP 130.5 MB
MPESTI Initiator Reference Design – User Guide
FPGA-RD-02341 1.0 5/14/2026 PDF 4.5 MB

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