Mach-N2

Hardware Security for Programmable System Control

Related Products

Related Applications

The Lattice Mach-N2 family of small, secure control FPGAs delivers up to 220k System Logic Cells of density with integrated non-volatile flash, and offers small package options. Built using the Lattice Nexus 2 platform, the family is optimized for low power relative to the competition and delivers best-in-class device security with CNSA 2.0-compliant, post-quantum-ready protection in its class.

Integrated Security – PUF, user run-time security, and CNSA 2.0-compliant, post-quantum cryptography with crypto agility on the Root-of-Trust device.

Integrated Flash and Instant-on – On-chip non-volatile flash for configuration and data storage, protecting the bitstream from physical access and enabling single-chip boot in under 30 ms.

Low Power – Built on the low power Lattice Nexus 2 platform.

Features

  • Features up to 220k System Logic Cells, 12 Mb embedded memory, and 520 – 18 x 18 multipliers
  • Integrated non-volatile flash for secure configuration and data storage, with single-chip instant-on boot
  • Hardware Root of Trust with Physically Unclonable Function (PUF) for DICE and SPDM attestation, and post-quantum cryptography (RoT device)
  • CNSA 2.0-compliant cryptography with crypto agility to adjust to evolving security standards
  • Class leading bitstream encryption (AES-256-GCM) and authentication (ECDSA / RSA)

Jump to

Family Table

Mach-N2 Device Selection Guide
Features MH06 MH10 MH16 MH20 MH21D
System Logic Cells (k) 65 100 160 220 215
Look-Up-Tables (k LUTs) 40 61 98 135 132
Embedded Memory (EBR) Blocks (36 kb) 114 153 228 306 289
Embedded Memory (Mb) 4 5.5 8 12 10.4
Distributed RAM Bits (kb) 416 636 1041 1400 1370
DSP (18 x 18 Multipliers) 120 240 360 520 520
High Frequency Oscillator (400 MHz) 1 1 1 1 1
GPLL 4 4 7 7 7
External Memory Interface support LPDDR4 / DDR4
Temperature Grades1 C, I C, I C, I C, I C, I
Bitstream Encryption / Authentication AES-256-GCM / ECDSA / RSA
Post-Quantum Cryptography (PQC) / Crypto Agility — — — — Supported
0.8 mm Total I/O (Wide Range / High Performance) / SERDES

MH06 MH10 MH16 MH20 MH21D
CBG256 (FCCSP, 14 × 14 mm, 0.8 mm) 141 (39, 102) / 2 141 (39, 102) / 2 — — —
CBG484 (FCCSP, 18 × 18 mm, 0.8 mm) 196 (92, 104) / 4 196 (92, 104) / 4 248 (92, 156) / 4 248 (92, 156) / 4 236 (83, 153) / 4

1. C=Commercial, I=Industrial

Block Diagram

Secure System Control

  • Instant-on boot for first-on, last-off system protection
  • Post-quantum safe key exchange and PUF
  • Physical security with embedded flash and programmable anti-tamper response

Network Switch

  • Aggregates control signals over PCIe
  • Offload real-time monitoring and management of SFPs from network CPU
  • Secure authentication of components

Securing Datapath

  • In-line 10GbE data encryption and decryption
  • Secure key exchange with processor
  • Secure key storage and update

Videos

Lattice Mach™-N2 as a Network Interface Card: PCIe Gen4 x4 to Gigabit Ethernet Bridge

This demo showcases the Lattice Mach-N2™ FPGA functioning as a Network Interface Card (NIC), bridging data transfer between a PCIe Gen4 x4 interface and a Triple-Speed Ethernet (TSE) MAC RGMII interface. The demonstration highlights high-speed data movement, efficient protocol bridging, and the flexibility of Mach-N2 devices for networking and connectivity applications.

Date: October 21, 2026 (English) Watch Now

Lattice Mach™-N2 DQ CNSA 2.0 Support: Post-Quantum Cryptography with ML-DSA and AES-256

This demo showcases the Lattice Mach-N2 Post-Quantum Cryptography (PQC) solution implemented on a Lattice Mach-N2 RoT Series FPGA. The demonstration highlights quantum-resistant security using ML-DSA (FIPS 204) for key generation, digital signing, and signature verification to authenticate messages, and ML-KEM (FIPS 203) for secure key establishment to protect the device root of trust against future quantum-based attacks. For data confidentiality, the design also incorporates AES-256 encryption and decryption. Together, these engines implement the CNSA 2.0-approved quantum-resistant algorithm suite, delivering crypto-agile, post-quantum-ready security in a compact, low power FPGA platform.

Date: October 21, 2026 (English) Watch Now

Lattice Security Solutions Portfolio including Lattice Mach™-N2, Lattice Sentry™ 5, Lattice Security Retrofit, and Nuvoton OpenTitan

This presentation provides an overview of the Lattice security portfolio for data center platforms, including Lattice Mach-N2, Lattice Sentry 5, the Security Retrofit approach, and the Lattice and Nuvoton OpenTitan solution. It shows how each option helps customers add Root of Trust capabilities to new and existing designs.

Date: October 21, 2026 (English) Watch Now

Design Resources

Development Kits & Boards

Our development boards & kits help streamline your design process

Intellectual Property & Reference Designs

Simplify your design efforts by using pre-tested, reusable functions

Software

Complete Design Flows, High Ease of Use

Documentation

Quick Reference
Technical Resources
Information Resources
Downloads
TITLENUMBERVERSIONDATEFORMATSIZE
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I3C Target Driver API Reference
FPGA-TN-023381.19/17/2026PDF604.9 KB
Lattice Nexus 2 Platform - Overview Data Sheet
FPGA-DS-021220.809/17/2026PDF1.5 MB
Lattice Nexus 2 Platform Data Sheet - Specifications
FPGA-DS-021210.809/17/2026PDF2.2 MB
Lattice Nexus 2 Power User Guide
FPGA-TN-023810.819/17/2026PDF497.2 KB
Lattice Nexus 2 SERDES/PCS User Guide
FPGA-TN-023950.819/17/2026PDF1.9 MB
Lattice Nexus 2 sysCLOCK PLL Design and User Guide
FPGA-TN-023640.829/17/2026PDF1.6 MB
Lattice OrCAD Capture Schematic Library
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.
FPGA-SC-020059.39/17/2026ZIP3.4 MB
Minimizing System Interruption During Configuration Using TransFR Technology
FPGA-TN-021984.79/17/2026PDF1.8 MB
PCB Layout Recommendations for BGA Packages
FPGA-TN-020245.79/17/2026PDF6.8 MB
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-020282.79/17/2026PDF748 KB
Thermal Management
FPGA-TN-020446.19/17/2026PDF1.2 MB
TITLENUMBERVERSIONDATEFORMATSIZE
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Lattice Nexus 2 Platform - Overview Data Sheet
FPGA-DS-021220.809/17/2026PDF1.5 MB
Lattice Nexus 2 Platform Data Sheet - Specifications
FPGA-DS-021210.809/17/2026PDF2.2 MB
TITLENUMBERVERSIONDATEFORMATSIZE
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I3C Target Driver API Reference
FPGA-TN-023381.19/17/2026PDF604.9 KB
Lattice Nexus 2 Configuration Security User Guide
Access this document via a Technical Support Request after signing in to the Lattice website. Complete the request form via this link, please click here.
FPGA-TN-023690.819/17/2026WEB
Lattice Nexus 2 Device Security User Guide
Access this document via a Technical Support Request after signing in to the Lattice website. Complete the request form via this link, please click here.
FPGA-TN-023680.819/17/2026WEB
Lattice Nexus 2 Embedded Memory User Guide
FPGA-TN-023660.829/17/2026PDF1.1 MB
Lattice Nexus 2 Hardware Checklist
FPGA-TN-023820.839/17/2026PDF1.1 MB
Lattice Nexus 2 High-Speed I/O and External Memory Interface User Guide
FPGA-TN-023720.829/17/2026PDF1.6 MB
Lattice Nexus 2 Multi-Boot User Guide
FPGA-TN-023850.819/17/2026PDF1.7 MB
Lattice Nexus 2 Power User Guide
FPGA-TN-023810.819/17/2026PDF497.2 KB
Lattice Nexus 2 SED/SEC User Guide
FPGA-TN-023800.819/17/2026PDF617.4 KB
Lattice Nexus 2 SERDES/PCS User Guide
FPGA-TN-023950.819/17/2026PDF1.9 MB
Lattice Nexus 2 sysCLOCK PLL Design and User Guide
FPGA-TN-023640.829/17/2026PDF1.6 MB
Lattice Nexus 2 sysCONFIG User Guide
FPGA-TN-023700.829/17/2026PDF3.5 MB
Lattice Nexus 2 sysDSP User Guide
FPGA-TN-023620.839/17/2026PDF935.5 KB
Lattice Nexus 2 sysI/O User Guide
FPGA-TN-023650.829/17/2026PDF729.5 KB
Mach-N2 Evaluation Board
FPGA-EB-020780.819/17/2026PDF4.6 MB
Minimizing System Interruption During Configuration Using TransFR Technology
FPGA-TN-021984.79/17/2026PDF1.8 MB
PCB Layout Recommendations for BGA Packages
FPGA-TN-020245.79/17/2026PDF6.8 MB
Sub-LVDS Signaling Using Lattice Devices
FPGA-TN-020282.79/17/2026PDF748 KB
Thermal Management
FPGA-TN-020446.19/17/2026PDF1.2 MB

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Lattice Nexus 2 Package Diagram
FPGA-DS-021240.829/17/2026ZIP250.5 KB
Mach-N2 MH20/16 Pinout Table
FPGA-SC-021240.809/17/2026CSV21.8 KB
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I3C Target IP Core - User Guide
FPGA-IPUG-022271.79/17/2026PDF2.4 MB
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Lattice OrCAD Capture Schematic Library
This file contains an OrCAD Capture Schematic Library (OLB file type) for all Lattice products. This .zip file also includes a .xls worksheet with a list of the contents of the OLB. These symbols can be used to help with OrCAD schematic designs.
FPGA-SC-020059.39/17/2026ZIP3.4 MB
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I3C Target IP Core - Release Notes
FPGA-RN-020181.39/17/2026PDF393.3 KB
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Mach-N2 MH16 BSDL Model File
FPGA-MD-021290.809/17/2026ZIP10.3 KB
Mach-N2 MH20 BSDL Model File
FPGA-MD-021300.809/17/2026ZIP10.3 KB
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Lattice Nexus 2 Delphi Models
FPGA-MD-020750.829/17/2026ZIP43.5 KB
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Mach-N2 IBIS Model file
FPGA-MD-021281.09/17/2026ZIP28.6 MB