8N1 UART Transceiver Reference Design

8-bit data, no parity, 1 stop bit Universal Asynchronous Receiver/Transmitter

8-bit data, no parity, and 1 stop bit - Universal Asynchronous Receiver/Transmitter (UART) performs serial-to-parallel and parallel to serial conversions on data characters received from a peripheral device or CPU. It operates at fixed 8-bit data, no parity, and 1 stop bit.

Configurable FIFO option - Both UART transmitter and receiver have a configurable FIFO option for better throughput. The FIFO buffer utilizes the Lattice Semiconductor DPRAM (Dual Port Random Access Memory) IP, whose depth can be configured using Lattice Radiant™ IP Catalog, Lattice Diamond® IPexpress, or Clarity Designer.

Complete Reference Design - implemented in Verilog. Training dataset, project & source files and test bench are provided to enable modification.

Features

  • 8-bit data, no parity, 1 stop bit (8N1)
  • Optional FIFO buffer for both UART transmitter and receiver
  • Configurable FIFO buffer depth
  • Configurable baud rate
  • Verilog RTL, testbench, and Aldec A-HDL script for simulation

Block Diagram

Documentation

Technical Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
8N1 UART Tranceiver - Source Code
1.0 5/1/2021 ZIP 1.9 MB
8N1 UART Tranceiver - Documentation
FPGA-RD-02196 1.0 5/1/2021 PDF 954.7 KB
8N1 UART Tranceiver Demo - Documentation
FPGA-UG-02118 1.0 5/1/2021 PDF 739.1 KB
8N1 UART Tranceiver Demo - Source Code
1.0 5/1/2021 ZIP 748.7 KB

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