UART 16550 IP Core

​​Serial Communications Receiver and Transmitter IP​

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​​The Lattice Semiconductor UART (Universal Asynchronous Receiver/Transmitter) 16550 IP is designed for use in serial ​communication, supporting the RS-232, RS-422, RS-485, and Electronic Industries Association (EIA) standards, among ​others.

Compatible with the National Semiconductor PC16550D UART – ​ The register set, data transfer protocol, and interrupt generation of this IP is compatible with the National Semiconductor PC16550D UART with integrated transmit and receive FIFOs which relieves the Host of excessive overhead.​

Receiver and Transmitter Design Features – The design features a receiver (serial to parallel converter) and a transmitter (parallel to serial converter), each controlled separately.

​​Configurable Baud Rate Support for Standard and Custom Modes​​ – In Standard mode, programmable divisor latch for baud rates provides fixed pre-defined values. In Custom mode, Baud Rate accepts any value from range 1-999999.​

Features

  • FIFO mode transmitter and receiver, each are buffered with the 16-bytes FIFO to reduce the CPU overhead.
  • Configurable stop bits – 1 or 2 bits for transmit operations.
  • Configurable data widths of 5, 6, 7, or 8 bits.
  • Verilog RTL test bench.

Resource Utilization details are available in the IP Core User Guide.

Block Diagram

Resource Utilization

Device Clk Fmax (MHz)* Slice Registers LUTs EBRs
iCE40UP5K 52.507 674 1281 0
LIFCL-40 168.209 653 841 0

Ordering Information

Available for free to use in Lattice Radiant design software.

Documentation

Quick Reference
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
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UART 16550 IP Core - User Guide
FPGA-IPUG-02100 1.4 4/7/2024 PDF 946.5 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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UART 16550 IP Core
1.0 4/10/2018 IPK 277.1 KB
UART 16550 IP Core User Guide
FPGA-IPUG-02035 1.3 12/10/2019 PDF 1.2 MB

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