UART 16550 IP Core

Serial communications receiver and transmitter IP

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The Lattice Semiconductor UART (Universal Asynchronous Receiver/Transmitter) 16550 IP Core is designed for use in serial communication, supporting the RS-232, RS-422, RS-485, and Electronic Industries Association (EIA) standards, among others. The design features a receiver (serial to parallel converter) and a transmitter (parallel to serial converter), each controlled separately. The register set, data transfer protocol, and interrupt generation of this IP Core is compatible with the National Semiconductor PC16550D UART with integrated transmit and receive FIFOs which relieves the Host of excessive overhead.

Features

  • Compatible with National Semiconductor PC16550D UART (NS-PC16550D)
  • Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data
  • Independently controlled transmit, receive, line status, and data set interrupts
  • MODEM control functions (CTS, RTS, DSR, DTR, RI, and DCD)
  • FIFO mode transmitter and receiver, each are buffered with 16-bytes FIFO to reduce the CPU overhead

Block Diagram

iCE40 UltraPlus UART IP top Level Diagram

Resource Utilization

Device Clk Fmax (MHz)* Slice Registers LUTs EBRs
iCE40UP5K 52.507 674 1281 0
LIFCL-40 168.209 653 841 0

Ordering Information

Available for free to use in Lattice Radiant design software.

Documentation

Quick Reference
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
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UART 16550 IP Core - Lattice Radiant Software
FPGA-IPUG-02100 1.3 6/23/2021 PDF 1.1 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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UART 16550 IP Core
1.0 4/10/2018 IPK 277.1 KB
UART 16550 IP Core User Guide
FPGA-IPUG-02035 1.3 12/10/2019 PDF 1.2 MB

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