Lattice Solutions

Reference Design

I2C Bus Master

Demonstrates how a fast and configurable I2C-Bus Master Controller can be constructed and utilized in a Lattice CPLD/FPGA device

MachXO, LatticeXP2, ispMACH 4000ZE, MachXO2, LatticeECP3, Platform Manager, ECP5 / ECP5-5G, MachXO3 

Bus Controllers, I2C, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, 5G 

Reference Design

UART Reference Design

The UART reference design describes a fully configurable UART optimized for and implemented in a variety of Lattice devices.

ispMACH 4000ZE, MachXO, LatticeXP2, Platform Manager, MachXO5-NX, MachXO2 

Bus Controllers, UART 

Reference Design

SDR SDRAM Controller-Advanced Reference Design

Provides a simple generic system interface to the bus master, reducing the user's effort to deal with the SDRAM command interface.

MachXO, ispMACH 4000ZE, LatticeXP2, MachXO2, LatticeECP3, ECP5 / ECP5-5G, MachXO3 

DDR SDRAM 

Board

ispMACH 4256ZE Breakout Board

A simple low-cost board that provides complete I/O access to the ispMACH4256ZE (TN144 package)+LEDs, Prototyping area and more.

ispMACH 4000ZE 

Breakout 

Reference Design

BSCAN - Multiple Port Linker (BSCAN2)

Implements an IEEE 1149.1 compliant Boundary Scan port on an FPGA. Multiple scan ports are linked together feeing into the IEEE 1149.1 port.

MachXO, MachXO2, ispMACH 4000ZE, ispMACH 4000V/B/C/Z, LatticeXP2, ECP5 / ECP5-5G 

IEEE 1149.1, Boundary Scan 

Reference Design

I2C Bus Controller for Serial EEPROMs

Provides an interface between standard microprocessors and I2C Serial EEPROM devices

MachXO, LatticeXP2, ispMACH 4000ZE, MachXO2, LatticeECP3, ECP5 / ECP5-5G, MachXO3 

Bus Controllers, I2C 

Reference Design

I2C Slave/Peripheral

Implements an I2C slave module in a FPGA or CPLD. Follows the I2C specification to provide device addressing, read/write operation and acknowledgment

LatticeECP3, LatticeXP2, MachXO, Platform Manager, ispMACH 4000ZE, ECP5 / ECP5-5G 

I2C, TOR Switch, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets 

Reference Design

SPI Controller - WISHBONE Compatible

Provides an interface between a microprocessor with a WISHBONE bus and external SPI devices.

ispMACH 4000ZE, MachXO, LatticeXP2, MachXO2, MachXO3 

SPI, Wishbone, TOR Switch 

Reference Design

LPC (Low Pin Count) Bus Controller

Implements a Low Pin Count bus controller - based on the Intel Low Pin Count Interface Specification (version 1.1)

MachXO2, LatticeXP2, LatticeECP3, ispMACH 4000ZE, MachXO 

Bus Controllers, LPC, Signal Aggregation, TOR Switch 

Reference Design

Read and Write Usercode

Read or change a Usercode or User Electronic Signature (UES) through general I/O without reprogramming the entire on-device Flash or interrupting the system.

ispMACH 4000ZE, MachXO, MachXO2, MachXO3 

Security, UES 

Reference Design

BSCAN - Multiple Port Addressable Buffer (BSCAN-1)

A multiple boundary scan test access port (TAP) addressable buffer function that can be accessed through a standard IEEE 1149.1 interface

LatticeXP2, ispMACH 4000ZE, MachXO, ispMACH 4000V/B/C/Z, Platform Manager 

Boundary Scan, IEEE 1149.1, TOR Switch 

Reference Design

PCI Target 32-bit/33MHz

Fully Compliant with PCI 2.2 specification.

ispMACH 4000ZE, MachXO, LatticeXP2, LatticeECP3 

Bus Controllers, PCI, Defense 

Reference Design

SPI GPIO Expander

Expand microprocessor general purpose I/O ports with a Serial Peripheral Interface (SPI)

Platform Manager, MachXO, ispMACH 4000ZE 

GPIO Control, Signal Aggregation, Soft Processor, SPI, TOR Switch 

Reference Design

GPIO Expander

Provides a solution that uses a Lattice PLD as a GPIO Expander

LatticeECP3, MachXO, LatticeXP2, ispMACH 4000ZE, Platform Manager 

GPIO Control, Signal Aggregation, TOR Switch 

Reference Design

HDLC Controller

Implements HDLC (High-Level Data Link Control), located at the OSI link layer 2. supports LAPB, LAPD, LLC and SDLC with a few modifications

LatticeECP2/M, ispMACH 4000V/B/C/Z, ispMACH 4000ZE, LatticeXP2, MachXO 

Data Communication, Ethernet 

Reference Design

PWM Fan Controller - WISHBONE Compatible

Implements a PWM fan control using a PLD and a MOSFET circuit to provide the speed control of a simple 2-pin or 3-pin fan.

ispMACH 4000ZE, MachXO, LatticeXP2, MachXO2, MachXO3, ispMACH 4000V/B/C/Z 

PWM, Wishbone, TOR Switch 

Reference Design

SPI Peripheral

Implements a Serial Peripheral Interface (SPI) slave device interface that provides full-duplex, synchronous, serial communication with a SPI master

MachXO, ispMACH 4000ZE, Platform Manager 

Bus Controllers, SPI, TOR Switch 

Reference Design

Wake on LAN Reference Design

WoL allows a load/client on a network to be turned on by a message sent via the network, saving power by keeping the device in stand-by mode until needed.

ispMACH 4000ZE, MachXO 

Ethernet, Power Management 

Reference Design

Fast Page Mode DRAM Controller

Implements a Fast Page Mode (FPM) DRAM Controller

ispMACH 4000ZE 

FPM DRAM 

Reference Design

Standard SDRAM Controller for ispMACH Devices

SDRAM Interface to standard microprocessors, independent of the processor type. The design as shown supports two 16MB memory regions configured as 4 M x 32 bits

ispMACH 4000ZE, ispMACH 4000V/B/C/Z 

SDRAM