| Device Family |
Tested Devices* |
Performance |
I/O Pins |
Design Size |
Revision |
| ECP5™ 6 |
LFE5U-45F-
6MG285C |
>50MHz |
18 |
85 LUTs (Verilog Source)
85 LUTs (VHDL Source) |
2.6 |
| LatticeECP3™ 3 |
LFE3-17EA-
6FTN256C |
>50MHz |
18 |
96 LUTs (Verilog Source)
94 LUTs (VHDL Source) |
2.6 |
| MachXO3L™ 7 |
LCMXO3L-4300C-
6BG256C |
>50MHz |
18 |
85 LUTs (Verilog-LSE Source)
84 LUTs (Verilog-Syn Source) |
2.6 |
84 LUTs (Verilog-LSE Source)
86 LUTs (Verilog-Syn Source) |
2.6 |
| MachXO2™ 1 |
LCMXO2-1200HC-
6TG144C |
>50MHz |
18 |
86 LUTs (Verilog Source)
85 LUTs (VHDL Source) |
2.6 |
| MachXO™ 2 |
LCMXO256E-
3T100C |
>50MHz |
18 |
82 LUTs (Verilog Source)
82 LUTs (VHDL Source) |
2.6 |
| LatticeP2™ 4 |
LFXP2-5E-
5M132C |
>50MHz |
18 |
89 LUTs (Verilog Source)
90 LUTs (VHDL Source) |
2.6 |
| ispMACH® 4000ZE 5 |
LC4256ZE-
5TN100C |
>50MHz |
18 |
89 Macrocells (Verilog Source)
90 Macrocells (VHDL Source) |
2.6 |
* May work in other devices as well.
Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.