PCI Target 32-bit/33MHz

This 33MHz 32-Bit PCI Target Reference Design has been optimized for use in Lattice's PLDs. This PCI Target design is used to interface a Back End Device that doesn't support the PCI protocol to the PCI Bus. The Back End interface can be modified to meet the requirements of the interfacing system. Using the design's fully-developed and automated test bench to verify its functionality will get both new and experienced designers up and running fast. This design conforms to the PCI 2.2 specification.

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Block Diagram

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Performance and Size

Tested Devices* Performance I/O Pins Design Size Revision
LCMXO2280C-5FT256C >70MHz 111 213 LUTs 3.3
LC4512V-35FT256C >70MHz 111 285/512 Macrocells 3.3
LFE3-70E-8FN484C >33 MHz 111 250 LUTs 3.4
LFXP2-5E-5FT256C >33 MHz 111 252 LUTs 3.4

* May work in other devices as well.

Note: The performance and design sizes shown above are estimates only. The actual results may vary depending upon the chosen parameters, timing constraints, and device implementation. See the design's documentation for details. All coding and design work was done on a PC platform unless noted otherwise.


Technical Resources
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PCI Target 32-bit/33MHz
FPGA-RD-02134 3.6 1/31/2021 PDF 1.8 MB
PCI Target (33MHz, 32 Bit ) - Source Code
RD1008 3.5 8/20/2013 ZIP 980.4 KB

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