Tri-Speed Ethernet MAC IP Core

Configurable Ethernet Controller

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Tri-Speed Ethernet Media Access Controller (TSEMAC) IP core is a complex core containing all necessary logic, interfacing and clocking infrastructure to integrate an external industry-standard Ethernet PHY with an internal processor efficiently and with minimal overhead.

The TSEMAC IP core supports the ability to transmit and receive data between the standard interfaces, such as APB, AHB-Lite or AXI4-Lite, and an Ethernet network. The main function of TSEMAC IP is to ensure that the Media Access rules specified in the 802.3 IEEE standard are met while transmitting a frame of data over Ethernet. On the receiving side, the TSEMAC extracts different components of a frame and transfers them to higher applications through the FIFO interface.

Features

  • Compliant to IEEE 802.3-2005 standard
  • 8-bit wide internal data path
  • Full-duplex operation in 1G mode
  • Full- and half-duplex operation in 10/100 mode
  • Option to select between MAC only and MAC + PHY mode (only available in Avant)

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Block Diagram

Tri-State Ethernet

Performance and Size

Avant (LAV-AT-500E-1LFG1156I)
Configuration Fmax (MHz)1
clk_i		 Fmax (MHz)1
rxmac_clk_i		 Fmax (MHz)1
txmac_clk_i		 Registers LUTs EBRs
Select IP Option: MAC+PHY (default) Others = Default 192 - - 3764 4764 5
Host Interface: AHBL,
Others = Default		 200 - - 3741 5000 5
Host Interface: APB,
Others = Default		 203 - - 3640 4738 5
Select MAC + PHY Operating
Option: Gigabit Ethernet,
Others = Default		 192 - - 3645 4764 5
Select IP Option: MAC ONLY Others = Default 198 221 206 1826 2342 4
Host Interface: AHBL,
Others = Default		 153 176 161 1826 2462 4
Host Interface: APB,
Others = Default		 153 167 165 1917 2747 4
Select MAC Operating
Option: Gigabit MAC,
Others = Default		 164 185 159 1821 2435 4
Select MAC Operating
Option: SGMII Easy Connect,
Others = Default		 162 251 187 1777 2308 4
Select MAC Operating
Option: RGMII,
Others = Default		 151 240 164 1807 2454 4

1. Fmax is generated when the FPGA design only contains Tri-Speed Ethernet MAC IP Core, and the target frequency for clk_i, rxmac_clk_i, and txmac_clk_i are 100 MHz, 125 MHz, and 125 MHz, respectively. These values may be reduced when user logic is added to the FPGA design.

ECP5 (LFE5U)1
Configuration SLICEs LUTs REGs EBRs External
Pins		 fMAX (MHz)
MIIM Module Operation Mode
No Classic 1245 1694 1193 2 25 125
No Gigabit 1080 1430 1061 1 22 125
No SGMII 1249 1696 1173 2 4 125
Yes Classic 1408 1849 1345 2 27 125
Yes Gigabit 1263 1582 1213 1 24 125
Yes SGMII 1423 1857 1325 2 6 125

1. Performance and utilization data are generated targeting an LFE5U-85F-8BG756C device using Lattice Diamond 3.2 and Synplify Pro for Lattice I-2013.09L-SP1-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the Sapphire family.

ECP5 (LFE5UM)1
Configuration SLICEs LUTs REGs EBRs External
Pins		 fMAX (MHz)
MIIM Module Operation Mode2
No Classic 1245 1694 1193 2 25 125
No Gigabit 1080 1430 1061 1 22 125
No SGMII 1249 1696 1173 2 4 125
Yes Classic 1408 1849 1345 2 27 125
Yes Gigabit 1263 1582 1213 1 24 125
Yes SGMII 1423 1857 1325 2 6 125

1. Performance and utilization data are generated targeting an LFE5UM-85F-8BG756C device using Lattice Diamond 3.2 and Synplify Pro for Lattice I-2013.09L-SP1-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the Sapphire family.

LatticeECP31
Configuration SLICEs LUTs REGs EBRs External
Pins		 fMAX (MHz)
MIIM Module Operation Mode
No Classic 1232 1721 1193 2 25 125
No Gigabit 1037 1427 1061 1 22 125
No SGMII 1227 1718 1173 2 4 125
Yes Classic 1355 1872 1345 2 27 125
Yes Gigabit 1186 1596 1213 1 24 125
Yes SGMII 1371 1881 1325 2 6 125

1. Performance and utilization data are generated targeting an LFE3-95EA-8FN484C device using Lattice Diamond 3.2 and Synplify Pro for Lattice I-2013.09L-SP1-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family.

LatticeXP21
Configuration SLICEs LUTs REGs EBRs External
Pins		 fMAX (MHz)
MIIM Module Operation Mode2
No Classic 1337 1855 1197 2 25 125
No GbE 1086 1450 1061 1 22 125
Yes Classic 1494 3031 1352 2 27 125
Yes GbE 1243 1620 1213 1 24 125

1. Performance and utilization data are generated targeting an LFXP2-17E-6F484C device using Lattice Diamond 3.2 and Synplify Pro for Lattice I-2013.09L-SP1-1 software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeXP2 family.
2. The SGMII Easy Connect option is only available on device families with SERDES I/O.

Ordering Information

Device Family Part Numbers
Single Design Multi-Site Subscription
Avant-E TS-MAC-AVE-U TS-MAC-AVE-UT TS-MAC-AVE-US
MachXO5-NX TS-MAC-XO5-U TS-MAC-XO5-UT TS-MAC-XO5-US
CertusPro-NX TS-MAC-CPNX-U TS-MAC-CPNX-UT TS-MAC-CPNX-US
Certus-NX TS-MAC-CTNX-U TS-MAC-CTNX-UT TS-MAC-CTNX-US
CrossLink-NX TS-MAC-CNX-U TS-MAC-CNX-UT TS-MAC-CNX-US
ECP5 TS-MAC-E5-U TS-MAC-E5-UT TS-MAC-E5-US
LatticeECP3 TS-MAC-E3-U4 TS-MAC-E3-UT4 -
LatticeXP2 TS-MAC-X2-U4 TS-MAC-X2-UT4 -
LatticeECP2 TS-MAC-P2-U4 TS-MAC-P2-UT4 -
LatticeECP2M TS-MAC-PM-U4 TS-MAC-PM-UT4 -
LatticeEC/ECP TS-MAC-E2-U4 TS-MAC-E2-UT4 -
LatticeSC/M TS-MAC-PM-U4 TS-MAC-PM-UT4 -
LatticeXP TS-MAC-XM-U4 TS-MAC-XM-UT4 -

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

To find out how to purchase the Tri-speed Ethernet MAC IP core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
LatticeMico32 Tri-Speed Ethernet MAC Gigabit Demo for the LatticeECP3 Versa Evaluation Board User's Guide
UG47 01.0 4/15/2011 PDF 2.1 MB
Tri-Speed Ethernet MAC IP Core - Lattice Radiant Software
FPGA-IPUG-02084 1.6 12/5/2022 PDF 1.7 MB
Tri-Speed Ethernet MAC User's Guide
IPUG51 3.3 4/4/2015 PDF 5.4 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
LatticeECP3 Versa - TSMAC Demo - Design Files for Windows
1.0 5/22/2013 EXE 5.8 MB
Tri-Speed Ethernet MAC Demo
8/6/2006 ZIP 5.5 MB

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