Tri-Speed Ethernet MAC IP Core

Configurable Ethernet Controller

Tri-Speed Ethernet Media Access Controller (TSEMAC) IP core is a complex core containing all necessary logic, interfacing and clocking infrastructure to integrate an external industry-standard Ethernet PHY with an internal processor efficiently and with minimal overhead.

The TSEMAC IP core supports the ability to transmit and receive data between the standard interfaces, such as APB, AHB-Lite or AXI4-Lite, and an Ethernet network. The main function of TSEMAC IP is to ensure that the Media Access rules specified in the 802.3 IEEE standard are met while transmitting a frame of data over Ethernet. On the receiving side, the TSEMAC extracts different components of a frame and transfers them to higher applications through the FIFO interface.

Features

  • Compliant to IEEE 802.3-2005 standard
  • 8-bit wide internal data path
  • Full-duplex operation in 1G mode
  • Full- and half-duplex operation in 10/100 mode
  • Option to select between MAC only and MAC + PHY mode (only available in Avant)

Jump to

Block Diagram

Resource Utilization

Resource Utilization for Avant Family
LAV-AT-500E-3LFG1156I
Configuration Fmax (MHz)1 clk_i Fmax (MHz)1 rxmac_clk_i Fmax (MHz)1 txmac_clk_i Registers LUTs EBRs
Select IP Option:
MAC+PHY
(default)
Others = Default 250 - - 3602 4949 5
Host Interface: AHBL,
Others = Default
250 - - 3693 5178 5
Host Interface: APB,
Others = Default
253 - - 3586 4889 5
Select MAC + PHY Operating Option: Gigabit Ethernet,
Others = Default
250 - - 3602 4949 5
Select IP Option:
MAC ONLY
Others = Default 198 221 206 1826 2342 4
Host Interface: AHBL,
Others = Default
153 176 161 1826 2462 4
Host Interface: APB,
Others = Default
153 167 165 1917 2747 4
Select MAC Operating Option: Gigabit MAC,
Others = Default
164 185 159 1821 2435 4
Select MAC Operating Option: SGMII Easy Connect,
Others = Default
162 251 187 1777 2308 4
Select MAC Operating Option: RGMII,
Others = Default
151 240 164 1807 2454 4
Statistics Counter Option: Checked,
Others = Default
170 183 171 5468 8443 4

Note:
1. Fmax is generated when the FPGA design only contains Tri-Speed Ethernet MAC IP Core, and the target frequency for clk_i, rxmac_clk_i, and txmac_clk_i are 100 MHz, 125 MHz, and 125 MHz, respectively. These values may be reduced when user logic is added to the FPGA design.

For Nexus Family
LIFCL-40-9BG400I
Configuration Fmax (MHz)* clk_i Fmax (MHz)* rxmac_clk_i Fmax (MHz)* txmac_clk_i Registers LUTs EBRs
Default 135 163.452 158.128 1579 2740 4
Classic MAC 135 163.452 158.128 1579 2740 4
Gbit MAC 144.613 158.078 182.183 1540 2600 4
SGMII Easy connect 145.201 172.028 178.508 1566 2723 4
RGMII 151.86 163.934 158.579 1587 2688 4
LFD2NX-40-9BG256I
Configuration Fmax (MHz)* clk_i Fmax (MHz)* rxmac_clk_i Fmax (MHz)* txmac_clk_i Registers LUTs EBRs
Default 145.645 142.653 160.746 1579 2735 4
Classic MAC 145.645 142.653 160.746 1579 2735 4
Gbit MAC 144.175 159.261 178.413 1540 2600 4
SGMII Easy connect 145.117 164.366 177.399 1566 2723 4
RGMII 147.929 165.755 167.813 1587 2688 4

*Note:Fmax is generated when the FPGA design only contains tri-speed Ethernet Media Access Controller IP Core and the target Frequency is 100 MHz. These values may be reduced when user logic is added to the FPGA design.

To view the complete Resource Utilization of the Tri-Speed Ethernet MAC IP Core, click here to view the table.

Ordering Information

Device Family Part Numbers
Single Design Multi-Site Subscription
Avant-E TS-MAC-AVE-U TS-MAC-AVE-UT TS-MAC-AVE-US
MachXO5-NX TS-MAC-XO5-U TS-MAC-XO5-UT TS-MAC-XO5-US
CertusPro-NX TS-MAC-CPNX-U TS-MAC-CPNX-UT TS-MAC-CPNX-US
Certus-NX TS-MAC-CTNX-U TS-MAC-CTNX-UT TS-MAC-CTNX-US
CrossLink-NX TS-MAC-CNX-U TS-MAC-CNX-UT TS-MAC-CNX-US
ECP5 TS-MAC-E5-U TS-MAC-E5-UT TS-MAC-E5-US
LatticeECP3 TS-MAC-E3-U4 TS-MAC-E3-UT4 -
LatticeXP2 TS-MAC-X2-U4 TS-MAC-X2-UT4 -
LatticeECP2 TS-MAC-P2-U4 TS-MAC-P2-UT4 -
LatticeECP2M TS-MAC-PM-U4 TS-MAC-PM-UT4 -
LatticeEC/ECP TS-MAC-E2-U4 TS-MAC-E2-UT4 -
LatticeSC/M TS-MAC-PM-U4 TS-MAC-PM-UT4 -
LatticeXP TS-MAC-XM-U4 TS-MAC-XM-UT4 -

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

To find out how to purchase the Tri-speed Ethernet MAC IP core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
LatticeMico32 Tri-Speed Ethernet MAC Gigabit Demo for the LatticeECP3 Versa Evaluation Board User's Guide
UG47 01.0 4/15/2011 PDF 2.1 MB
Tri-Speed Ethernet MAC IP Core - User Guide
FPGA-IPUG-02084 1.8 1/17/2024 PDF 2.9 MB
Tri-Speed Ethernet MAC User's Guide
IPUG51 3.3 4/4/2015 PDF 5.4 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Tri-Speed Ethernet MAC Demo
8/6/2006 ZIP 5.5 MB
LatticeECP3 Versa - TSMAC Demo - Design Files for Windows
1.0 5/22/2013 EXE 5.8 MB

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