Tri-Speed Ethernet Media Access Controller (TSEMAC) IP core is a complex core containing all necessary logic, interfacing and clocking infrastructure to integrate an external industry-standard Ethernet PHY with an internal processor efficiently and with minimal overhead.
The TSEMAC IP core supports the ability to transmit and receive data between the standard interfaces, such as APB, AHB-Lite or AXI4-Lite, and an Ethernet network. The main function of TSEMAC IP is to ensure that the Media Access rules specified in the 802.3 IEEE standard are met while transmitting a frame of data over Ethernet. On the receiving side, the TSEMAC extracts different components of a frame and transfers them to higher applications through the FIFO interface.