Tri-Speed Ethernet MAC IP Core

Configurable Ethernet Controller

Related Products

Tri-Speed Ethernet Media Access Controller (TSEMAC) IP core is a complex core containing all the necessary logic, interfacing, and clocking infrastructure to integrate an external industry-standard Ethernet PHY with an internal processor efficiently and with minimal overhead.

Resource Utilization details are available in the IP Core User Guide.

Features

  • ​​Compliant to IEEE 802.3-2005 standard.​
  • ​​​​8-bit wide internal data path.​
  • ​​​​Full-duplex operation in 1G mode.​
  • ​​​​Full- and half-duplex operation in 10/100M mode.​
  • ​​Transmit and receive statistics vector and statistic counter.

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Block Diagram

Tri-Speed Ethernet MAC IP Core Block DiagramExpand Image

Resource Utilization

Resource Utilization for an Avant Device (LAV-AT-E70-1LFG676I)
Configuration Fmax (MHz)* clk_i Fmax (MHz)* rxmac_clk_i Fmax (MHz)* txmac_clk_i Registers LUTs EBRs
Select IP Option:
MAC+PHY
(default)		 Others = Default 250 - - 4460 12048 3
Select MAC + SGMII
Operating Option:
Gigabit Ethernet,
Others = Default		 250 - - 4378 12002 3
Select IP Option:
MAC Only		 Others = Default 242 207 197 2106 7609 4
Host Interface: AHBL,
Others = Default		 242 198 200 2197 7865 4
Host Interface: APB,
Others = Default		 238 197 205 2099 7554 4
Select MAC Operating Option: Gigabit MAC,
Others = Default		 224 200 197 1971 7301 2
Select MAC Operating Option: SGMII Easy Connect,
Others = Default		 229 214 208 2002 7466 2
Select MAC Operating Option: RGMII,
Others = Default		 220 191 194 2127 7593 4
Select MAC Operating Option: RMII,
Others = Default		 183 206 207 2163 7641 4
Statistics Counter Option: Checked,
Others = Default		 176 207 204 5774 10803 4

Note:
* Fmax is generated when the FPGA design only contains the Tri-Speed Ethernet MAC IP core, and the target frequency for clk_i, rxmac_clk_i, and txmac_clk_i is 125 MHz. These values may be reduced when user logic is added to the FPGA design.

Resource Utilization for a CertusPro-NX Device (LFCPNX-50-7ASG256I)
Configuration Fmax (MHz)* clk_i Fmax (MHz)* rxmac_clk_i Fmax (MHz)* txmac_clk_i Registers LUTs EBRs
Select IP Option:
MAC+PHY
(default)		 Others = Default 166 - - 3503 4675 6
Select IP Option:
MAC Only		 Others = Default 168 136 153 2019 2879 6
Host Interface: AHBL,
Others = Default		 181 133 145 2110 3089 6
Host Interface: APB,
Others = Default		 164 144 154 2012 2823 6
Select MAC Operating Option: Gigabit MAC,
Others = Default		 157 141 150 1865 2604 4
Select MAC Operating Option: SGMII Easy Connect,
Others = Default		 183 153 154 1896 2741 4
Select MAC Operating Option: RGMII,
Others = Default		 153 129 138 2040 2885 6
Select MAC Operating Option: RMII,
Others = Default		 176 139 145 2077 2960 6
Statistics Counter Option: Checked,
Others = Default		 127 142 151 5696 6264 6

Note:
* Fmax is generated when the FPGA design only contains the Tri-Speed Ethernet MAC IP core, and the target frequency for clk_i, rxmac_clk_i, and txmac_clk_i is 125 MHz. These values may be reduced when user logic is added to the FPGA design.

Ordering Information

  Part Number
Device Family Multi-site Perpetual Single Seat Annual
Avant-G TS-MAC-AVG-UT TS-MAC-AVG-US
Avant-X TS-MAC-AVX-UT TS-MAC-AVX-US
Avant-E TS-MAC-AVE-UT TS-MAC-AVE-US
CrossLink-NX TS-MAC-CNX-UT TS-MAC-CNX-US
CertusPro-NX TS-MAC-CPNX-UT TS-MAC-CPNX-US
Certus-NX TS-MAC-CTNX-UT TS-MAC-CTNX-US
MachXO5-NX TS-MAC-XO5-UT TS-MAC-XO5-US
ECP5 TS-MAC-E5-UT TS-MAC-E5-US
LatticeECP3 TS-MAC-E3-UT4 TS-MAC-E3-US
LatticeECP2 TS-MAC-P2-UT4 -
LatticeECP2M TS-MAC-PM-UT4 TS-MAC-PM-US
LatticeEC/ECP TS-MAC-E2-UT4 -
LatticeSC/M TS-MAC-SC-UT4 -
LatticeXP2 TS-MAC-X2-UT4 -
LatticeXP TS-MAC-XM-UT4 -

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

To find out how to purchase the Tri-speed Ethernet MAC IP core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Triple-Speed Ethernet MAC Driver API Reference
FPGA-TN-02341 1.1 7/29/2024 PDF 398.2 KB
Tri-Speed Ethernet MAC IP Core - User Guide
FPGA-IPUG-02084 2.1 9/23/2024 PDF 4.6 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Triple-Speed Ethernet MAC Driver API Reference
FPGA-TN-02341 1.1 7/29/2024 PDF 398.2 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
LatticeMico32 Tri-Speed Ethernet MAC Gigabit Demo for the LatticeECP3 Versa Evaluation Board User's Guide
UG47 01.0 4/15/2011 PDF 2.1 MB
Tri-Speed Ethernet MAC IP Core - User Guide
FPGA-IPUG-02084 2.1 9/23/2024 PDF 4.6 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
LatticeECP3 Versa - TSMAC Demo - Design Files for Windows
1.0 5/22/2013 EXE 5.8 MB
Tri-Speed Ethernet MAC Demo
8/6/2006 ZIP 5.5 MB

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